PIC16C773-I/SP Microchip Technology, PIC16C773-I/SP Datasheet - Page 70

• Manufacturer Part Number: PIC16C773-I/SP
• Description: IC MCU OTP 4KX14 A/D PWM 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C773-I/SP

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 22
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16C773-04I/SP

PIC16C77X
8.2.3
While in sleep mode, the I
addresses or data, and when an address match or
complete byte transfer occurs wake the processor from
sleep (if the SSP interrupt is enabled).
TABLE 8-3
DS30275A-page 70
Legend:
Note 1:
0Bh, 8Bh,
10Bh,18Bh
0Ch
8Ch
0Dh
8Dh
13h
14h
91h
94h
Address
2:
SLEEP OPERATION
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I
These bits are reserved on the 28-pin devices, always maintain these bits clear.
These bits are reserved on these devices, always maintain these bits clear.
SSPCON2
INTCON
PIR1
PIE1
PIR2
PIE2
SSPBUF
SSPCON
SSPSTAT
Name
REGISTERS ASSOCIATED WITH I
Synchronous Serial Port Receive Buffer/Transmit Register
PSPIE
PSPIF
LVDIE
WCOL
GCEN
LVDIF
Bit 7
SMP
GIE
2
(1)
(1)
C module can receive
AKSTAT
SSPOV
ADIE
Bit 6
PEIE
ADIF
CKE
—
—
SSPEN
Advance Information
AKDT
RCIE
Bit 5
RCIF
T0IE
D/A
—
—
AKEN
INTE
Bit 4
TXIF
TXIE
CKP
—
—
P
2
SSPM3
SSPIE
SSPIF
BCLIF
BCLIE
RCEN
C OPERATION
RBIE
Bit 3
S
8.2.4
A reset diables the SSP module and terminates the
current transfer.
CCP1IF
CCP1IE
SSPM2
Bit 2
T0IF
PEN
R/W
—
—
EFFECTS OF A RESET
TMR2IE
TMR2IF
SSPM1
RSEN
INTF
Bit 1
UA
—
—
TMR1IF
TMR1IE
CCP2IE
CCP2IF
SSPM0
RBIF
Bit 0
SEN
BF
1999 Microchip Technology Inc.
2
C mode.
0000 000x
0000 0000
0000 0000
0--- 0--0
0--- 0--0
xxxx xxxx
0000 0000
0000 0000
0000 0000
POR, BOR
MCLR, WDT
0000 000u
0000 0000
0000 0000
0--- 0--0
0--- 0--0
uuuu uuuu
0000 0000
0000 0000
0000 0000