PIC18LF258-I/SP Microchip Technology, PIC18LF258-I/SP Datasheet - Page 305

IC MCU FLASH 16KX16 LV CAN 28DIP

PIC18LF258-I/SP

Manufacturer Part Number
PIC18LF258-I/SP
Description
IC MCU FLASH 16KX16 LV CAN 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF258-I/SP

Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Oscillator Type
External
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
22
Eeprom Memory Size
256Byte
Ram Memory Size
1536Byte
Cpu Speed
40MHz
No.
RoHS Compliant
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
22
Number Of Timers
4 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF258-I/SP
Manufacturer:
Microchip Technology
Quantity:
135
INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
CNT
If CNT
PC
If CNT
PC
Q1
Q1
Q1
=
=
=
=
=
register ‘f’
operation
operation
operation
(f) + 1
The contents of register ‘f’ are
Increment f, Skip if 0
[ label ]
0
d
a
skip if result = 0
None
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0011
No
No
No
Q2
Q2
Q2
f
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
[0,1]
[0,1]
255
by a 2-word instruction.
dest,
INCFSZ
INCFSZ
:
:
11da
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
f [,d [,a]]
ffff
CNT
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
REG
If REG
PC
If REG
PC
Q1
Q1
Q1
=
=
=
=
=
register ‘f’
operation
operation
operation
Increment f, Skip if not 0
[ label ]
0
d
a
(f) + 1
skip if result
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value (default).
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
f
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
[0,1]
[0,1]
PIC18FXX8
255
3 cycles if skip and followed
by a 2-word instruction.
dest,
INFSNZ
INFSNZ REG
10da
operation
operation
operation
Process
0
Data
No
No
No
Q3
Q3
Q3
DS41159E-page 303
f [,d [,a]]
ffff
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff

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