DSPIC30F4012-30I/SP Microchip Technology, DSPIC30F4012-30I/SP Datasheet - Page 66

IC DSPIC MCU/DSP 48K 28DIP

DSPIC30F4012-30I/SP

Manufacturer Part Number
DSPIC30F4012-30I/SP
Description
IC DSPIC MCU/DSP 48K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F4012-30I/SP

Program Memory Type
FLASH
Program Memory Size
48KB (16K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
20
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F401230ISP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4012-30I/SP
Manufacturer:
TI
Quantity:
17 600
Part Number:
DSPIC30F4012-30I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F4011/4012
FIGURE 9-1:
9.1
The 16-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal T
increment the respective timer when the gate input sig-
nal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.
9.2
The input clock (F
Timer, has a prescale option of 1:1, 1:8, 1:64, and
1:256
(T1CON<5:4>). The prescaler counter is cleared when
any of the following occurs:
• a write to the TMR1 register
• clearing of the TON bit (T1CON<15>)
• device Reset such as POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register.
DS70135C-page 64
selected
Timer Gate Operation
Timer Prescaler
SOSCO/
SOSCI
T1IF
Event Flag
T1CK
OSC
by
/4 or external clock) to the 16-bit
16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)
control
TGATE
0
1
Reset
Equal
bits
LPOSCEN
Comparator x 16
TCKPS<1:0>
TMR1
PR1
CY
Preliminary
to
Q
Q
Gate
Sync
CK
T
D
CY
9.3
During CPU Sleep mode, the timer will operate if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
• The TSYNC bit (T1CON<2>) is asserted to a logic
When all three conditions are true, the timer will con-
tinue to count up to the period register and be reset to
0x0000.
When a match between the timer and the period regis-
ter occurs, an interrupt can be generated, if the
respective Timer Interrupt Enable bit is asserted.
TGATE
(TCS = 1) and
0, which defines the external clock source as
asynchronous
Timer Operation During Sleep
Mode
1 X
0 0
0 1
TON
(3)
TSYNC
 2005 Microchip Technology Inc.
0
1
1, 8, 64, 256
TCKPS<1:0>
Prescaler
Sync
2

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