ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet - Page 128

IC AVR MCU 16K 8MHZ 1.8V 40DIP

ATMEGA162V-8PU

Manufacturer Part Number
ATMEGA162V-8PU
Description
IC AVR MCU 16K 8MHZ 1.8V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA162V-8PU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG/SPI/USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA162V-8PU
Manufacturer:
IDT
Quantity:
74
16-bit
Timer/Counter
Register
Description
Timer/Counter1
Control Register A –
TCCR1A
Timer/Counter3
Control Register A –
TCCR3A
128
ATmega162/V
• Bit 7:6 – COMnA1:0: Compare Output Mode for channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for channel B
The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respec-
tively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OCnA or OCnB pin must be set in order to enable the output driver.
When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen-
dent of the WGMn3:0 bits setting.
WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).
Table 53. Compare Output Mode, non-PWM
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
COMnA1/
COMnB1
0
0
1
1
COM1A1
COM3A1
R/W
R/W
7
0
7
0
COMnA0/
COMnB0
0
1
0
1
COM1A0
COM3A0
R/W
R/W
6
0
6
0
Description
Normal port operation, OCnA/OCnB disconnected.
Toggle OCnA/OCnB on Compare Match.
Clear OCnA/OCnB on Compare Match (Set output to low level).
Set OCnA/OCnB on Compare Match (Set output to high level).
COM1B1
COM3B1
R/W
R/W
5
0
5
0
Table 53
COM1B0
COM3B0
R/W
R/W
4
0
4
0
shows the COMnx1:0 bit functionality when the
FOC1A
FOC3A
W
W
3
0
3
0
FOC1B
FOC3B
W
W
2
0
2
0
WGM11
WGM31
R/W
R/W
0
0
1
1
WGM10
WGM30
R/W
R/W
0
0
0
0
TCCR1A
TCCR3A
2513K–AVR–07/09

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