PIC18F2480-I/SO Microchip Technology, PIC18F2480-I/SO Datasheet - Page 4

• Manufacturer Part Number: PIC18F2480-I/SO
• Description: IC PIC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2480-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2480/2580/4480/4580
5. Module: ECAN™ Technology
6. Module: ECAN™ Technology
EXAMPLE 4:
DS80219E-page 4
Under specific conditions, the first five bits of a
transmitted identifier may not match the value in
the Transmit Buffer ID register, TXBnSIDH. The
following conditions must exist for the corruption to
occur:
1. A transmit message must be pending.
2. The ECAN module must detect a Start-of-
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
The Error Interrupt Flag, ERRIF (PIR3<5>), may
not be able to clear in software after either of the
following counter registers exceeds 127.
• Transmit Error Counter Register TXERRCNT
• Receive Error Counter Register RXERRCNT
Work around
Monitor the EWARN (COMSTAT<0>) bit to deter-
mine if either the TXERRCNT or the RXERRCNT
exceeds 95 and clear the ERRIF flag before either
counter reaches 127.
Date Codes that pertain to this issue:
All engineering and production devices.
If (RXBnOVFL == 1)
Frame (SOF) in the third bit of interframe
space.
{
}
Temp_RXREG = RXBx;
If (MyFlag)
{
}
If (TXREQ == 1)
{
}
TXREQ = 1;
MyFlag = 0;
TXREQ = 0;
If (TXABT == 1)
MyFlag = 1;
// Has an overflow occurred?
// Is a transmission pending?
// Clear transmit request
// Store transmission aborted status value
// Read receive buffer
// Was previous transmission aborted?
// Set transmit request
// Reset stored transmission aborted status
7. Module: ECAN™ Technology
8. Module: ECAN™ Technology
Following an error on the bus, the ECAN module is
unable to switch from Listen Only mode directly to
Configuration mode.
Work around
Use the REQOP (CANCON<7:5>) bits to select
Normal mode as an intermediate step when
switching from Listen Only mode to Configuration
mode.
Date Codes that pertain to this issue:
All engineering and production devices.
Under specific conditions, the TXBnSIDH register
of the pending message for transmission may be
corrupted. The following conditions must exist for
this event to occur:
1. A transmit message must be pending.
2. All of the receive buffers must be full and a
3. A receiver buffer must be made available
Work around
Ensure that a receive buffer overflow condition
does not occur and/or ensure that a transmit
request is not pending if a receive buffer overflow
condition does exist.
The pseudo-code segment in Example 4 is an
example of how to disable a pending transmission.
This code is for illustration purposes only.
Date Codes that pertain to this issue:
All engineering and production devices.
received message is in the Message Assembly
Buffer (MAB).
(RXBxCON<RXFUL> set to '0') when a Start-
of-Frame (SOF) is recognized on the CAN bus,
or on the instruction cycle prior to the SOF for
the TXBxSIDH corruption event to occur. The
timing of this event is crucial.
© 2007 Microchip Technology Inc.