DSPIC30F5013-20E/PT Microchip Technology, DSPIC30F5013-20E/PT Datasheet - Page 17

• Manufacturer Part Number: DSPIC30F5013-20E/PT
• Description: IC DSPIC MCU/DSP 66K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5013-20E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F5013-20EP

35.3.3.2
Figure 35-7:
Figure 35-8:
Figure 35-9:
© 2008 Microchip Technology Inc.
SPI Master, Frame Master Mode
SPI Master, Frame Master Connection Diagram
SPI Master, Frame Master Timing (FRMDLY = 0)
SPI Master, Frame Master Timing (FRMDLY = 1)
(FRMPOL = 1)
(FRMPOL = 0)
(SPI1 Master, Framed Master)
(FRMPOL = 1)
(FRMPOL = 0)
Section 35. Serial Peripheral Interface (SPI) (Part II)
(CKP = 1)
(CKP = 0)
(CKP = 1)
(CKP = 0)
In the SPI Master/Frame Master mode, the SPI1 module generates both the clock and frame
synchronization signals, as shown in Figure 35-7. This configuration is enabled by setting the
MSTEN and FRMEN bits to ‘1’ and the SPIFSD bit to ‘0’.
In this mode, the serial clock is output continuously at the SCK1 pin regardless of whether the
module is transmitting. When SPI1BUF is written, the SS1 pin will be driven to its active state (as
determined by the FRMPOL bit) on the appropriate transmit edge of the SCK1 clock and remain
active for one data frame. If the FRMDLY control bit (SPI1CON2<1>) is cleared, the frame
synchronization pulse precedes the data transmission, as shown in Figure 35-8. If FRMDLY is
set, the frame synchronization pulse coincides with the beginning of the data transmission, as
shown in Figure 35-9. The module starts transmitting data on the next transmit edge of the SCK1.
Write to SPI1BUF
SDO1
SCK1
SCK1
SDO1
SCK1
SCK1
SDI1
SDI1
SS1
SS1
SS1
SS1
dsPIC30F
Write to SPI1BUF
SDO1
SCK1
SDI1
SS1
Pulse Generated at SS1
Frame Synchronization
Pulse
Serial Clock
bit 15
bit 15
bit 15
bit 15
SDI1
SDO1
SCK1
SS1
bit 14
bit 14
bit 14
bit 14
Pulse Generated by SS1;
Receive Samples at SDI1
Receive Samples at SDI1
PROCESSOR 2
bit 13
bit 13
bit 13
bit 13
bit 12
bit 12
bit 12
bit 12
DS70272B-page 35-17
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