DSPIC30F5013-20E/PT Microchip Technology, DSPIC30F5013-20E/PT Datasheet - Page 19

• Manufacturer Part Number: DSPIC30F5013-20E/PT
• Description: IC DSPIC MCU/DSP 66K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5013-20E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F5013-20EP

35.3.3.4
Figure 35-13: SPI Slave, Frame Master Connection Diagram
35.3.3.5
Figure 35-14: SPI Slave, Frame Slave Connection Diagram
© 2008 Microchip Technology Inc.
SPI Slave, Frame Master Mode
SPI Slave, Frame Slave Mode
(SPI1 Slave, Framed Master)
(SPI1 Slave, Framed Slave)
Section 35. Serial Peripheral Interface (SPI) (Part II)
In the SPI Slave/Frame Master mode, the module acts as the SPI slave and takes its clock from
the other SPI module; however, it produces frame synchronization signals to control data
transmission (Figure 35-13). This mode is enabled by setting the MSTEN bit to ‘0’, the FRMEN
bit to ‘1’ and the SPIFSD bit to ‘0’.
The input SPI clock will be continuous in Slave mode. The SS1 pin will be an output when the
SPIFSD bit is low. Therefore, when the SPI1BUF is written, the module drives the SS1 pin to the
active state on the appropriate transmit edge of the SPI clock for one SPI clock cycle. Data will
start transmitting on the appropriate SPI clock transmit edge.
In the SPI Slave/Frame Slave mode, the module obtains both its clock and frame synchronization
signal from the Master module (Figure 35-14). This mode is enabled by setting MSTEN to ‘0’,
FRMEN to ‘1’ and SPIFSD to ‘1’.
In this mode, both the SCK1 and SS1 pins will be inputs. The SS1 pin is sampled on the sample
edge of the SPI clock. When SS1 is sampled at its active state, data will be transmitted on the
appropriate transmit edge of SCK1.
dsPIC30F
dsPIC30F
SDO1
SCK1
SDO1
SCK1
SDI1
SDI1
SS1
SS1
Frame Synchronization
Pulse
Frame Synchronization
Pulse
Serial Clock
Serial Clock
SDI1
SDO1
SCK1
SS1
SDI1
SDO1
SCK1
SS1
PROCESSOR 2
PROCESSOR 2
DS70272B-page 35-19
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