PIC18F448-E/P Microchip Technology, PIC18F448-E/P Datasheet - Page 314
![IC MCU FLASH 8KX16 W/CAN 40-DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F448-E/P
Manufacturer Part Number
PIC18F448-E/P
Description
IC MCU FLASH 8KX16 W/CAN 40-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18LF242-ISO.pdf
(36 pages)
2.PIC18F248-ISO.pdf
(402 pages)
3.PIC18F248-ISO.pdf
(8 pages)
Specifications of PIC18F448-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F448-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS41159E-page 312
PIC18FXX8
Q Cycle Activity:
After Interrupt
operation
Decode
No
PC
W
BSR
Status
GIE/GIEH, PEIE/GIEL
Q1
operation
operation
Return from Interrupt
[ label ]
s
(TOS)
1
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged.
GIE/GIEH, PEIE/GIEL.
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers W, Status
and BSR. If ‘s’ = 0, no update of these
registers occurs (default).
1
2
RETFIE 1
0000
No
No
Q2
[0,1]
GIE/GIEH or PEIE/GIEL,
W,
PC,
RETFIE [s]
BSR,
0000
operation
operation
=
=
=
=
=
Status,
No
No
Q3
TOS
WS
BSRS
STATUSS
1
0001
Pop PC from
Set GIEH or
operation
stack
GIEL
No
Q4
000s
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
TABLE
Q Cycle Activity:
:
:
:
CALL TABLE ; W contains table
ADDWF PCL
RETLW k0
RETLW k1
RETLW kn
Before Instruction
After Instruction
operation
Decode
No
Q1
W
W
operation
; offset value
; W now has
; table value
; W = offset
; Begin table
;
; End of table
=
=
literal ‘k’
Return Literal to W
[ label ]
0
k
(TOS)
PCLATU, PCLATH are unchanged
None
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
1
2
Read
No
Q2
0000
k
0x07
value of kn
W,
© 2006 Microchip Technology Inc.
255
PC,
RETLW k
1100
operation
Process
Data
No
Q3
kkkk
from stack,
Write to W
operation
Pop PC
No
Q4
kkkk
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