AT90CAN32-16AU Atmel, AT90CAN32-16AU Datasheet - Page 370

IC MCU AVR 32K FLASH 64-TQFP

AT90CAN32-16AU

Manufacturer Part Number
AT90CAN32-16AU
Description
IC MCU AVR 32K FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Datasheets

Specifications of AT90CAN32-16AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT90CANx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
No. Of I/o's
53
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
4
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Figure 26-3. Two-wire Serial Bus Timing
26.6
370
2. Required only for f
3. C
4. f
5. This requirement applies to all AT90CAN32/64/128 Two-wire Serial Interface operation. Other devices connected to the
6. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/f
7. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/f
SPI Timing Characteristics
AT90CAN32/64/128
SCL
SDA
Two-wire Serial Bus need only obey the general f
greater than 6 MHz for the low time requirement to be strictly met at f
requirement will not be strictly met for f
bus may communicate at full speed (400 kHz) with other AT90CAN32/64/128 devices, as well as any other device with a
proper t
CK
b
= capacitance of one bus line in pF.
= CPU clock frequency
t
SU;STA
LOW
acceptance margin.
See
Table 26-4.
SCL
10
11
12
1
2
3
4
5
6
7
8
9
Figure 26-4
> 100 kHz.
t
HD;STA
t
t
of
SCK to out high
SCK high/low
LOW
Rise/Fall time
Rise/Fall time
SCK high/low
SS low to out
SPI Timing Parameters
Description
SCK period
SCK period
Out to SCK
SCK to out
and
Setup
Hold
SCL
Figure 26-5
> 308 kHz when f
t
HIGH
t
(1)
HD;DAT
SCL
requirement.
for details.
t
LOW
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
CK
= 8 MHz. Still, AT90CAN32/64/128 devices connected to the
t
SU;DAT
SCL
4 • t
2 • t
Min.
= 100 kHz.
ck
ck
See
50% duty cycle
0.5 • t
Table 16-4
t
Typ.
SU;STO
3.6
SCL
SCL
10
10
10
10
15
sck
t
r
- 2/f
- 2/f
CK
CK
), thus f
), thus the low time
t
BUF
Max.
7679H–CAN–08/08
CK
1.6
must be
ns
µs

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