DSPIC33FJ256GP710A-E/PF Microchip Technology, DSPIC33FJ256GP710A-E/PF Datasheet - Page 167
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DSPIC33FJ256GP710A-E/PF
Manufacturer Part Number
DSPIC33FJ256GP710A-E/PF
Description
IC DSPIC DSC 256K FLASH 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
2.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
3.DSPIC33FJ128GP306A-IPT.pdf
(350 pages)
Specifications of DSPIC33FJ256GP710A-E/PF
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
100-TQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
30 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM300019, DV164033, MA330011, MA330012, DM300024
Minimum Operating Temperature
- 40 C
Package
100TQFP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
64-chx10-bit|64-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256GP710A-E/PF
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
DSPIC33FJ256GP710A-E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ64GP206-IPT PDF datasheet
- DSPIC33FJ64GP206A-IMR PDF datasheet #2
- DSPIC33FJ128GP306A-IPT PDF datasheet #3
- Current page: 167 of 322
- Download datasheet (5Mb)
14.0
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33FJXXXGPX06/X08/X10 devices support
up to eight input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
1.
FIGURE 14-1:
© 2009 Microchip Technology Inc.
Note:
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
ICx Pin
Simple Capture Event modes
-Capture timer value on every falling edge of
-Capture timer value on every rising edge of
input at ICx pin
input at ICx pin
INPUT CAPTURE
This data sheet summarizes the features
of the dsPIC33FJXXXGPX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 12.
“Input
“dsPIC33F Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
Prescaler
(1, 4, 16)
Counter
Capture”
3
INPUT CAPTURE BLOCK DIAGRAM
System Bus
ICxCON
ICM<2:0> (ICxCON<2:0>)
ICOV, ICBNE (ICxCON<4:3>)
Mode Select
(DS70198)
dsPIC33FJXXXGPX06/X08/X10
Edge Detection Logic
Clock Synchronizer
ICxI<1:0>
and
in
the
(in IFSn Register)
Set Flag ICxIF
Interrupt
Logic
2.
3.
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Input capture can also be used to provide
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
additional sources of external interrupts
Note:
-Capture timer value on every 4th rising edge
-Capture timer value on every 16th rising
Capture timer value on every edge (rising and
falling)
Prescaler Capture Event modes
4 buffer locations are filled
of input at ICx pin
edge of input at ICx pin
Logic
FIFO
R/W
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to 1 (ICI<1:0> = 00).
From 16-bit Timers
TMRy TMRz
1
ICxBUF
16
0
DS70286C-page 165
16
ICTMR
(ICxCON<7>)
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