DSPIC33FJ256GP710A-E/PF Microchip Technology, DSPIC33FJ256GP710A-E/PF Datasheet - Page 179
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DSPIC33FJ256GP710A-E/PF
Manufacturer Part Number
DSPIC33FJ256GP710A-E/PF
Description
IC DSPIC DSC 256K FLASH 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
2.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
3.DSPIC33FJ128GP306A-IPT.pdf
(350 pages)
Specifications of DSPIC33FJ256GP710A-E/PF
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
100-TQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
30 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM300019, DV164033, MA330011, MA330012, DM300024
Minimum Operating Temperature
- 40 C
Package
100TQFP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
64-chx10-bit|64-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256GP710A-E/PF
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
DSPIC33FJ256GP710A-E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ64GP206-IPT PDF datasheet
- DSPIC33FJ64GP206A-IMR PDF datasheet #2
- DSPIC33FJ128GP306A-IPT PDF datasheet #3
- Current page: 179 of 322
- Download datasheet (5Mb)
17.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and
Multi-Master modes of the I
standard, with a 16-bit interface.
The dsPIC33FJXXXGPX06/X08/X10 devices have up
to two I
I2C2. Each I
pin is clock and the SDAx pin is data.
Each I
features:
• I
• I
• I
• I
• Serial clock synchronization for I
• I
17.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, please refer to the “dsPIC33F Family
Reference Manual”.
© 2009 Microchip Technology Inc.
Note:
operation.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and will arbitrate accordingly.
2
2
2
2
2
2
2
2
C interface supporting both master and slave
C Slave mode supports 7 and 10-bit address.
C Master mode supports 7 and 10-bit address.
C Port allows bidirectional transfers between
C supports multi-master operation; detects bus
C slave operation with 7-bit address
C slave operation with 10-bit address
C master operation with 7 or 10-bit address
2
2
C module can operate either as a slave or a
C module ‘x’ (x = 1 or 2) offers the following key
2
INTER-INTEGRATED
CIRCUIT™ (I
Operating Modes
C interface modules, denoted as I2C1 and
This data sheet summarizes the features
of the dsPIC33FJXXXGPX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 19.
“Inter-Integrated
(DS70195) in the “dsPIC33F Family
Reference Manual”, which is available
from
(www.microchip.com).
2
C module has a 2-pin interface: the SCLx
2
C bus.
the
2
C Standard and Fast mode
2
C operation are supported:
2
Microchip
C™)
2
C serial communication
2
Circuit™
C) module provides
2
C port can be
dsPIC33FJXXXGPX06/X08/X10
web
(I
2
C™)”
site
17.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
I2CxRSR is the shift register used for shifting data,
whereas I2CxRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CxRCV is the receive buffer. I2CxTRN is the transmit
register to which bytes are written during a transmit
operation.
The I2CxADD register holds the slave address. A
status bit, ADD10, indicates 10-bit Address mode. The
I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
I
2
C Registers
DS70286C-page 177
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