PIC18F2539-I/SP Microchip Technology, PIC18F2539-I/SP Datasheet - Page 16

• Manufacturer Part Number: PIC18F2539-I/SP
• Description: IC MCU FLASH 12KX16 EE A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2539-I/SP

• Core Size: 8-Bit
• Program Memory Size: 24KB (12K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.375KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Details

PIC18FXX39
3.4
Data EEPROM is accessed one byte at a time via an
Address Pointer, EEADR, and a data latch, EEDATA.
Data EEPROM is written by loading EEADR with the
desired memory location, EEDATA with the data to be
written, and initiating a memory write by appropriately
configuring the EECON1 and EECON2 registers. A
byte write automatically erases the location and writes
the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, the EEPGD bit must be cleared
(EECON1<7> = 0) and the CFGS bit must be cleared
(EECON1<6> = 0). The WREN bit must be set
(EECON1<2> = 1) to enable writes of any sort, and this
must be done prior to initiating a write sequence. The
write sequence is initiated by the setting the WR bit
(EECON1<1> = 1). It is strongly recommended that the
WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then, AAh, immediately prior to asserting the WR
bit in order for the write to occur.
The write will begin on the falling edge of the 4th SCLK
after the WR bit is set.
After the programming sequence terminates, SCLK
must still be held low for the time specified by
parameter P10 to allow high voltage discharge of the
memory array.
FIGURE 3-9:
DS30480C-page 16
SCLK
SDATA
Data EEPROM Programming
4-bit Command
1
0
2
0
3
0
4
0
P5
DATA EEPROM WRITE TIMING
BSF EECON1, WR
1
2
15 16
P5A
4-bit Command
1
0
2
0
3
0
Preliminary
SDATA = Input
4
0
P5
1
0
Data Payload
2
0
16-bit
FIGURE 3-8:
15 16
0
0
P5A
4-bit Command
1
0
2
No
0
3
0
Unlock Sequence
for Write to Occur
AAh - EECON2
Delay P11+P10
55h - EECON2
4
0
PROGRAM DATA FLOW
Enable Write
Set Address
Start Write
Sequence
 2010 Microchip Technology Inc.
Set Data
Done?
Start
Done
Data EEPROM
Yes
Write Time
P11
P10
Data Payload
16-bit
1
n
2
n