AT32UC3A3128-CTUR Atmel, AT32UC3A3128-CTUR Datasheet - Page 53
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AT32UC3A3128-CTUR
Manufacturer Part Number
AT32UC3A3128-CTUR
Description
IC MCU 128KB FLASH 144TBGA
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3A364-CTUR.pdf
(75 pages)
Specifications of AT32UC3A3128-CTUR
Package / Case
144-TBGA
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
66MHz
Number Of I /o
110
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, WDT
Connectivity
EBI/EMI, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB OTG
Core Size
32-Bit
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, I2S, JTAG, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
23
Number Of Timers
4
Operating Supply Voltage
- 0.3 V to + 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1104
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
10.9
These timings are given for worst case process, T = 85⋅C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance.
Table 10-18. SMC Clock Signal.
Note:
Table 10-19. SMC Read Signals with Hold Settings
Note:
32072AS–AVR32–03/09
Symbol
1/(t
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
CPSMC
1
2
3
4
5
7
8
9
10
11
12
13
14
16
17
18
EBI Timings
1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.
1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”.
)
Parameter
Data Setup before NRD High
Data Hold after NRD High
NRD High to NBS0/A0 Change
NRD High to NBS1 Change
NRD High to NBS2/A1 Change
NRD High to A2 - A23 Change
NRD High to NCS Inactive
NRD Pulse Width
Data Setup before NCS High
Data Hold after NCS High
NCS High to NBS0/A0 Change
NCS High to NBS0/A0 Change
NCS High to NBS2/A1 Change
NCS High to A2 - A23 Change
NCS High to NRD Inactive
NCS Pulse Width
Parameter
SMC Controller Clock Frequency
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
NRD Controlled (READ_MODE = 1)
NRD Controlled (READ_MODE = 0)
(nrd hold length - ncs rd hold length) * t
ncs rd hold length - nrd hold length)* t
ncs rd pulse length * t
ncs rd hold length * t
ncs rd hold length * t
ncs rd hold length * t
nrd pulse length * t
ncs rd hold length * t
nrd hold length * t
nrd hold length * t
nrd hold length * t
nrd hold length * t
11.5
Min
12
0
0
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
-
-
-
-
-
1.3
1.3
1.3
1.3
-
-
-
1.4
-
-
2.3
2.3
2.3
3.6
4
CPSMC
CPSMC
AT32UC3A3
1/(t
Max
-
-
cpcpu
1.3
2.3
(1)
)
Units
MHz
Units
ns
ns
53