DSPIC33FJ128MC710-E/PF Microchip Technology, DSPIC33FJ128MC710-E/PF Datasheet - Page 31
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DSPIC33FJ128MC710-E/PF
Manufacturer Part Number
DSPIC33FJ128MC710-E/PF
Description
IC DSPIC MCU/DSP 128K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ128MC710-E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP, 100-VQFP
For Use With
MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Figure 8-4 is a block diagram of the DCI module. The
DCI can support up to 16 time slots in a data frame for
a maximum frame size of 256 bits. There are control
FIGURE 8-4:
8.8
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface for communicating with
other peripheral or microcontroller devices such as
serial EEPROMs, shift registers, display drivers, A/D
Converters, etc. It is compatible with Motorola
SIOP interfaces.
This SPI module includes all SPI modes. A Frame
Synchronization mode is also included for support of
voice band codecs.
Four pins make up the serial interface: SDI, Serial Data
Input; SDO, Serial Data Output; SCK, Shift Clock Input
or Output; SS, Active-Low Slave Select, which also
serves as the FSYNC (Frame Synchronization Pulse).
A device set up as an SPI master provides the serial
communication clock signal on its SCK pin.
© 2005 Microchip Technology Inc.
SPI™ Module
Frame Length Selection bits
Transmit Buffer
Registers w/Shadow
Receive Buffer
Registers w/Shadow
Word Size Selection bits
DCI Mode Selection bits
DCI MODULE BLOCK DIAGRAM
F
OSC
/4
®
SPI and
Preliminary
BCG Control Bits
Synchronization
Sample Rate
Generator
Generator
Frame
15
bits for each time slot in the data frame that determine
whether the DCI will transmit/receive during the time
slot. The DCI module supports DMA data transfers.
A series of 8 or 16 clock pulses (depending on mode)
shift out the 8 or 16 bits (depending on whether a byte
or word is being transferred) and simultaneously shift in
8 or 16 bits of data from the SDI pin. An interrupt is
generated when the transfer is complete.
Slave select synchronization allows selective enabling
of SPI slave devices, which is particularly useful when
a single master is connected to multiple slaves.
The SPI1 and SPI2 modules support DMA data
transfers.
DCI Shift Register
Control Unit
DCI Buffer
CSCKD
COFSD
0
dsPIC33F
DS70155C-page 29
CSCK
COFS
CSDI
CSDO