DSPIC33FJ128MC710-E/PF Microchip Technology, DSPIC33FJ128MC710-E/PF Datasheet - Page 8
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DSPIC33FJ128MC710-E/PF
Manufacturer Part Number
DSPIC33FJ128MC710-E/PF
Description
IC DSPIC MCU/DSP 128K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ128MC710-E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP, 100-VQFP
For Use With
MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
dsPIC33F
2.0
The dsPIC33F device family employs a powerful 16-bit
architecture that seamlessly integrates the control
features
computational capabilities of a Digital Signal Processor
(DSP). The resulting functionality is ideal for
applications that rely on high-speed, repetitive
computations, as well as control.
The DSP engine, dual 40-bit accumulators, hardware
support for division operations, barrel shifter, 17 x 17
multiplier, a large array of 16-bit working registers and
FIGURE 2-1:
DS70155C-page 6
Legend:
Divide Control
Barrel Shifter
DSP Engine
ACCA<40>
ACCB<40>
dsPIC33F DEVICE FAMILY
OVERVIEW
MCU/DSP X-Data Path
DSP Y-Data Path
Address Path
of
a
Microcontroller
dsPIC33F DEVICE BLOCK DIAGRAM
17 x 17 Multiplier
W Register
16-bit ALU
Memory
Mapped
16 x 16
(MCU)
Array
with
Preliminary
the
X-Data Bus <16-bit>
Y-Data Bus <16-bit>
Prefetch & Decode
Program Counter
Status Register
Program Flash
Memory Data
Instruction
<23 bits>
X AGU
Access
Y AGU
a wide variety of data addressing modes, together
provide the dsPIC33F Central Processing Unit (CPU)
with extensive mathematical processing capability.
Flexible and deterministic interrupt handling, coupled
with a powerful array of peripherals, renders the
dsPIC33F devices suitable for control applications.
Further, Direct Memory Access (DMA) enables
overhead-free transfer of data between several
peripherals and a dedicated DMA RAM. Reliable, field
programmable
scalability of applications that use dsPIC33F devices.
Figure 2-1 shows a sample device block diagram
typical of the dsPIC33F product family.
23
24
Flash
Data SRAM
256 Kbytes
28 Kbytes
Dual Port
Program
2 Kbytes
Memory
Flash
RAM
up to
up to
© 2005 Microchip Technology Inc.
program
memory
Peripherals
Controller
I/O Ports
DMA
ensures