AT32UC3B064-A2UT Atmel, AT32UC3B064-A2UT Datasheet - Page 345
AT32UC3B064-A2UT
Manufacturer Part Number
AT32UC3B064-A2UT
Description
IC MCU AVR32 64KB FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B064-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
16KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
44
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP64-2 - STK600 SOCKET/ADAPTER FOR 64-TQFATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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•
•
Table 21-18.
•
Table 21-19.
•
Table 21-20.
32059I–06/2010
SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase
CHRL: Character Length.
USCLKS: Clock Selection
MODE
0
0
1
1
If USART does not operate in SPI Mode (MODE is … 0xE and 0xF):
SYNC = 0: USART operates in Asynchronous Mode.
SYNC = 1: USART operates in Synchronous Mode.
If USART operates in SPI Mode (MODE = 0xE or 0xF):
CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with
0
0
0
0
0
0
1
1
1
0
0
1
1
CPOL to produce the required clock/data relationship between master and slave devices.
USCLKS
CHRL
0
1
0
1
0
0
0
0
1
1
0
1
1
Note:
0
1
0
1
MODE
Others
1. The value of DIV is device dependent. Please refer to the Module Configuration section at the
Character Length
5 bits
6 bits
7 bits
8 bits
end of this chapter.
Selected Clock
CLK_USART
CLK_USART/DIV
Reserved
CLK
0
0
1
1
0
1
0
1
1
(1)
0
1
0
1
0
0
0
0
1
Mode of the USART
Normal
RS485
Hardware Handshaking
Modem
IS07816 Protocol: T = 0
IS07816 Protocol: T = 1
IrDA
SPI Master
SPI Slave
Reserved
AT32UC3B
345
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