AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 592
![IC MCU AVR32 512K FLASH 64TQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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27.4.5.1
27.4.5.2
27.4.5.3
27.4.6
32059I–06/2010
JTAG Interface
I/O Lines
Power Management
Clocks
The TMS, TDI, and TDO pins are multiplexed with I/O lines. When the JTAG is used the associ-
ated pins must be enabled. To enable the JTAG pins, refer to
While using the multiplexed JTAG lines all normal peripheral activity on these lines is disabled.
The user must make sure that no external peripheral is blocking the JTAG lines while
debugging.
When an instruction that accesses the SAB is loaded in the instruction register, before entering
a sleep mode, the system clocks are not switched off to allow debugging in sleep modes. This
can lead to a program behaving differently when debugging.
The JTAG Interface uses the external TCK pin as clock source. This clock must be provided by
the JTAG master.
Instructions that use the SAB bus requires the internal main clock to be running.
The JTAG Interface is accessed through the dedicated JTAG pins shown in
591. The TMS control line navigates the TAP controller, as shown in
The TAP controller manages the serial access to the JTAG Instruction and Data registers. Data
is scanned into the selected instruction or data register on TDI, and out of the register on TDO,
in the Shift-IR and Shift-DR states, respectively. The LSB is shifted in and out first. TDO is high-
Z in other states than Shift-IR and Shift-DR.
The device implements a 5-bit Instruction Register (IR). A number of public JTAG instructions
defined by the JTAG standard are supported, as described in
ber of 32-bit AVR-specific private JTAG instructions described in
instruction selects a specific data register for the Shift-DR path, as described for each
instruction.
Section
Section
Figure 27-5 on page
27.4.7.
27.5.2, as well as a num-
Section
AT32UC3B
Table 27-6 on page
27.5.3. Each
593.
592
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