ATMEGA128A-AU Atmel, ATMEGA128A-AU Datasheet

MCU 8BIT 128K ISP FLASH 64-TQFP

ATMEGA128A-AU

Manufacturer Part Number
ATMEGA128A-AU
Description
MCU 8BIT 128K ISP FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128A-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4784435

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Features
High-performance, Low-power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
– 128KBytes of In-System Self-programmable Flash program memory
– 4KBytes EEPROM
– 4KBytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Up to 64KBytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
– 2.7 - 5.5V
– 0 - 16MHz
Capture Mode
and Extended Standby
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
®
AVR
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 128KBytes
In-System
Programmable
Flash
ATmega128A
Summary
Rev. 8151HS–AVR–02/11

Related parts for ATMEGA128A-AU

ATMEGA128A-AU Summary of contents

Page 1

... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V • Speed Grades – 16MHz ® ® AVR 8-bit Microcontroller (1) 8-bit Microcontroller with 128KBytes In-System Programmable Flash ATmega128A Summary Rev. 8151HS–AVR–02/11 ...

Page 2

... The Pinout figure applies to both TQFP and MLF packages. The bottom pad under the QFN/MLF package should be soldered to ground. ® ® AVR ATmega128A is a low-power CMOS 8-bit microcontroller based on the AVR 48 PA3 (AD3) 47 PA4 (AD4) 46 PA5 (AD5) 45 PA6 (AD6) 44 PA7 (AD7) ...

Page 3

... GENERAL PURPOSE REGISTERS ALU STATUS REGISTER DATA REGISTER DATA DIR. PORTB REG. PORTB PORTB DRIVERS PB0 - PB7 ATmega128A PC0 - PC7 PORTC DRIVERS DATA REGISTER DATA DIR. PORTC REG. PORTC 8-BIT DATA BUS CALIB. OSC INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER OSCILLATOR TIMING AND ...

Page 4

... Atmel ATmega128A is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega128A AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...

Page 5

... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega128A as listed on page 73. ...

Page 6

... As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega128A as listed on page 81. ...

Page 7

... PEN has no function during normal operation. 8151HS–AVR–02/11 ® ® AVR ATmega103 compatibility mode, these pins only serves as strobes signals to the 324. Shorter pulses are not guaranteed to generate a reset. , even if the ADC is not used. If the ADC is used, it should be connected ATmega128A “System and Reset CC 7 ...

Page 8

... A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATmega128A 8 1. 8151HS–AVR–02/11 ...

Page 9

... RWWSRE BLBSET – – – – – – – – PORTG4 PORTG3 – – DDG4 DDG3 – – PING4 PING3 ATmega128A Bit 2 Bit 1 Bit 0 – – – – – – – – – – – – UCSZ11 UCSZ10 UCPOL1 UPE1 U2X1 ...

Page 10

... UCSR0A RXC0 $0A ($2A) UCSR0B RXCIE0 $09 ($29) UBRR0L $08 ($28) ACSR ACD $07 ($27) ADMUX REFS1 $06 ($26) ADCSRA ADEN $05 ($25) ADCH $04 ($24) ADCL $03 ($23) PORTE PORTE7 ATmega128A 10 Bit 6 Bit 5 Bit 4 Bit 3 PORTF6 PORTF5 PORTF4 PORTF3 DDF6 DDF5 DDF4 DDF3 – – – – SP14 ...

Page 11

... I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 8151HS–AVR–02/11 Bit 6 Bit 5 Bit 4 Bit 3 DDE6 DDE5 DDE4 DDE3 PINE6 PINE5 PINE4 PINE3 PINF6 PINF5 PINF4 PINF3 ATmega128A Bit 2 Bit 1 Bit 0 DDE2 DDE1 DDE0 PINE2 PINE1 PINE0 PINF2 PINF1 PINF0 Page ...

Page 12

... Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared ATmega128A 12 Operation Flags Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← ...

Page 13

... Set Negative Flag CLN Clear Negative Flag SEZ Set Zero Flag CLZ Clear Zero Flag SEI Global Interrupt Enable CLI Global Interrupt Disable 8151HS–AVR–02/11 ATmega128A then PC ← None then PC ← None Operation Flags then PC ← None then PC ← None Rd ← Rr None Rd+1:Rd ← ...

Page 14

... Set T in SREG CLT Clear T in SREG SEH Set Half Carry Flag in SREG CLH Clear Half Carry Flag in SREG MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break ATmega128A 14 S ← ← Operation Flags V ← ← ← ← ← ...

Page 15

... Tape & Reel 64A 64-lead 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 8151HS–AVR–02/11 (2) Ordering Code Package ATmega128A-AU 64A (3) ATmega128A-AUR 64A ATmega128A-MU 64M1 (3) ATmega128A-MUR 64M1 Package Type ATmega128A (1) Operation Range Industrial ...

Page 16

... JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega128A 16 B PIN 1 IDENTIFIER ...

Page 17

... Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 64M1, 64-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) ATmega128A C SEATING PLANE A1 A 0.08 C SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM NOTE A 0 ...

Page 18

... Errata The revision letter in this section refers to the revision of the ATmega128A device. 9.1 ATmega128A Rev. U • Wrong value for Version in the JTAG Device Identification Register • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer • ...

Page 19

... Update-DR. Problem Fix / Workaround – If ATmega128A is the only device in the scan chain, the problem is not visible. – Select the Device ID Register of the ATmega128A by issuing the IDCODE – If the Device IDs of all devices in the boundary scan chain must be captured 6 ...

Page 20

... Rev. 8151E – 02/ 10.5 Rev. 8151D – 07/ ATmega128A 20 Editing update according to the Atmel new style guide. No more space betweeen the numbers and their units. Updated the last page. Updated the table note of Table 27-3 on page and BODLEVEL=1 Inserted cross reference in “ ...

Page 21

... Rev. 8151A– 08/08 1. Updated “Errata” on page 375. ATmega128A Rev. U. Updated view of “Typical Characteristics” on page 337 Editorial updates. Initial revision. (Based on the ATmega128/L datasheet 2467R-AVR-06/08) Changes done compared to the ATmega128/L datasheet 2467R-AVR-06/08: - Updated “Stack Pointer” on page 13 - “ ...

Page 22

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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