PIC32MX575F512H-80I/PT Microchip Technology, PIC32MX575F512H-80I/PT Datasheet - Page 190

IC MCU 32BIT 512KB FLASH 64TQFP

PIC32MX575F512H-80I/PT

Manufacturer Part Number
PIC32MX575F512H-80I/PT
Description
IC MCU 32BIT 512KB FLASH 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr

Specifications of PIC32MX575F512H-80I/PT

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
CAN, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC32
No. Of I/o's
53
Ram Memory Size
64KB
Cpu Speed
80MHz
No. Of Timers
5
Digital Ic Case Style
TQFP
Embedded Interface Type
CAN, I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC32MX575F512H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC32MX575F512H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX575F512H-80I/PT
Manufacturer:
MICROCHI
Quantity:
20 000
Part Number:
PIC32MX575F512H-80I/PT
0
PIC32MX5XX/6XX/7XX
FIGURE 31-4:
DS61156B-page 190
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Internal Voltage Regulator Enabled
External V
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, XT, XTPLL and S
Note 1: The power-up period will be extended if the power-up sequence completes before the device
DDCORE
2: Includes interval voltage regulator stabilization delay.
3: Power-Up Timer (PWRT); only active when the internal voltage regulator is disabled.
Power-up Sequence
(Note 2)
Power-up Sequence
(Note 2)
(Note 3)
Power-up Sequence
exits from BOR (V
Provided
POWER-ON RESET TIMING CHARACTERISTICS
V
V
POR
POR
V
POR
DD
(Note 1)
(Note 1)
< V
(T
SY00
(T
SY00
PU
PU
DDMIN
)
)
(T
(T
(Note 1)
SY01
SYSDLY
SY02
PWRT
).
Preliminary
(T
SY10
OSC
)
OST
)
(T
SYSDLY
SY02
)
)
(T
CPU starts fetching code
SYSDLY
SY02
)
)
CPU starts fetching code
V
V
DD
DDCORE
CPU starts fetching code
V
V
DD
DD
 2009 Microchip Technology Inc.

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