ATMEGA649-16MU Atmel, ATMEGA649-16MU Datasheet - Page 164
ATMEGA649-16MU
Manufacturer Part Number
ATMEGA649-16MU
Description
IC AVR MCU FLASH 64K 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA649-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA649-16MU
Manufacturer:
Atmel
Quantity:
135
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18.4
164
Data Modes
ATmega329/3290/649/6490
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
18-3
nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
Table 18-3
Table 18-2.
Figure 18-3. SPI Transfer Format with CPHA = 0
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
and
Figure
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
and
MSB first (DORD = 0)
LSB first (DORD = 1)
CPOL Functionality
Table
18-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-
18-4, as done below:
MSB
LSB
Sample (Falling)
Sample (Rising)
Leading Edge
Setup (Falling)
Setup (Rising)
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Sample (Falling)
Sample (Rising)
Setup (Falling)
Setup (Rising)
Trailing eDge
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
SPI Mode
LSB
MSB
0
1
2
3
2552K–AVR–04/11
Figure
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