ATMEGA649-16MU Atmel, ATMEGA649-16MU Datasheet - Page 264
ATMEGA649-16MU
Manufacturer Part Number
ATMEGA649-16MU
Description
IC AVR MCU FLASH 64K 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA649-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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ATMEGA649-16MU
Manufacturer:
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Quantity:
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25.7
264
ATmega329/3290/649/6490 Boundary-scan Order
ATmega329/3290/649/6490
Table 25-7
scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit
scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of
Port A is scanned in the opposite bit order of the other ports. Exceptions from the rules are the
Scan chains for the analog circuits, which constitute the most significant bits of the scan chain
regardless of which physical pin they are connected to. In
to FF0, PXn. Control corresponds to FF1, and PXn. Pull-up_enable corresponds to FF2. Bit 4, 5,
6 and 7 of Port F is not in the scan chain, since these pins constitute the TAP pins when the
JTAG is enabled.
Table 25-7.
Bit Number
197
196
195
194
and
ATmega329/649 Boundary-scan Order, 64-pin
Signal Name
AC_IDLE
ACO
ACME
AINBG
Table 25-8
shows the Scan order between TDI and TDO when the Boundary-
Module
Comparator
Figure
25-3, PXn. Data corresponds
2552K–AVR–04/11
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