AT32UC3A1128-AUT Atmel, AT32UC3A1128-AUT Datasheet - Page 722
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AT32UC3A1128-AUT
Manufacturer Part Number
AT32UC3A1128-AUT
Description
IC MCU AVR32 128KB FLASH 100TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A1128-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Controller Family/series
AT32UC3A
No. Of I/o's
69
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Package
100TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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sample_clk
34.3
Figure 34-1. Functional Block Diagram
34.4
Table 34-1.
34.5
34.5.1
34.5.2
32058J–AVR32–04/11
din1[15:0]
din2[15:0]
Pin Name
DATA0
DATA1
DATAN0
DATAN1
Block Diagram
Pin Name List
Product Dependencies
clk
I/O Lines
Power Management
I/O Lines Description
The output pins used for the output bitstream from the Audio Bitstream DAC may be multiplexed
with PIO lines.
Before using the Audio Bitstream DAC, the PIO controller must be configured in order for the
Audio Bitstream DAC I/O lines to be in Audio Bitstream DAC peripheral mode.
The PB-bus clock to the Audio Bitstream DAC is generated by the power manager. Before using
the Audio Bitstream DAC, the programmer must ensure that the Audio Bitstream DAC clock is
enabled in the power manager.
Clock Generator
Equalization FIR
Equalization FIR
Pin Description
Output from Audio Bitstream DAC Channel 0
Output from Audio Bitstream DAC Channel 1
Inverted output from Audio Bitstream DAC Channel 0
Inverted output from Audio Bitstream DAC Channel 1
Audio Bitstream DAC
(INT=128)
(INT=128)
COMB
COMB
Sigma-Delta
Sigma-Delta
DA-MOD
DA-MOD
AT32UC3A
Output
Output
Output
Output
Type
bit_clk
bit_out1
bit_out2
722
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