PIC32MX695F512L-80I/PT Microchip Technology, PIC32MX695F512L-80I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC32MX695F512L-80I/PT
• Description: IC MCU 32BIT 512KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX695F512L-80I/PT

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX6xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX575/675/695/775/795
TABLE 1:
TABLE 2:
DS80480E-page 2
PIC32MX775F256L
PIC32MX575F512L
PIC32MX675F512L
PIC32MX695F512L
PIC32MX775F512L
PIC32MX795F512L
Note 1:
Note 1:
Compare
Compare
Compare
Ethernet
Module
Parallel
Master
Output
Output
Output
Timers
UART
I
DMA
ADC
USB
CAN
CAN
CAN
2
Port
SPI
SPI
C™
2:
The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
Refer to the “PIC32MX Flash Programming Specification” (DS61145) for detailed information on Device
and Revision IDs for your specific device.
Only those issues indicated in the last column apply to the current silicon revision.
Part Number
External Clock
Start condition
Pattern Match
Frame Slave
Specification
RMII 10 MB
Slave Mode
Input Mode
Generation
PWM Fault
Electrical
USB PLL
SILICON DEVREV VALUES (CONTINUED)
SILICON ISSUE SUMMARY
Feature
Interrupt
PWM
Mode
—
—
—
—
—
Number
Item
10.
12.
13.
14.
15.
16.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
The I
performing a Start condition.
Pause frames are sent at 10x the normal rate.
The interrupt generated by the module cannot be cleared
when the module is disabled.
A PMP interrupt used to wake the device will not be reflected
in the interrupt flag until the end of the write strobe.
OC Fault detection is not asynchronous.
The SPIBUSY and SRMT bits assert 1 bit time before the end
of the transaction.
The TXBF bit deasserts one PB clock after the interrupt is
generated.
The USBPLL does not automatically suspend in Idle mode.
In PWM mode, the output waveform is one PB clock longer
than the expected value.
A Fault interrupt will not be generated if firmware clears the
Fault while the Fault is still asserted.
In Pattern Match mode, the DMA module may not append all
of the CRC results to the result buffer.
In Synchronized External Clock mode, the first period of the
count is short.
Outgoing data corruption occurs when the frame signal is
coincident with the clock.
TXABAT, TXLARB and TXERR may erroneously be cleared
by an aborted read of the CiFIFOCONn register.
Requested aborts to a TX message via setting CxCON.ABAT
or clearing CiFIFOCON.TXREQ may not complete.
The CFIFOCONx.FRESET and CFIFOCONx.UINC bits are
not settable via a normal SFR write.
2
C modules may encounter a bus collision when
Device ID
0x4312053
0x430F053
0x4341053
0x4307053
0x4307053
0x4311053
(1)
Issue Summary
Revision ID for Silicon Revision
© 2010 Microchip Technology Inc.
0x0
0x0
0x0
0x0
0x0
0x0
A0
Revisions
Affected
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(2)
(1)