PIC32MX695F512L-80I/PT Microchip Technology, PIC32MX695F512L-80I/PT Datasheet - Page 7

• Manufacturer Part Number: PIC32MX695F512L-80I/PT
• Description: IC MCU 32BIT 512KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX695F512L-80I/PT

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX6xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18. Module: Output Compare
19. Module: SPI
20. Module: USB
21. Module: USB
© 2010 Microchip Technology Inc.
The Output Compare module may reinitialize or
clear a Fault on an aborted read of the OCxCON
register. An aborted read occurs when a read
instruction in the CPU pipeline has started
execution, but is aborted due to an interrupt.
Work around
Disable interrupts before reading the contents of
the OCxCON register, and then re-enable
interrupts after reading the register.
Affected Silicon Revisions
In Slave mode with TXISEL = 0, a TX buffer
underrun condition will not assert the TX interrupt
flag.
Work around
None.
Affected Silicon Revisions
The TOKBUSY bit does not correctly indicate sta-
tus when a transfer completes within the Start of
Frame threshold.
Work around
Use a firmware semaphore to track when a token
is written to U1TOK. Firmware then clears the
semaphore when the transfer is complete.
Affected Silicon Revisions
In Host mode, the interval between the first two
SOF packets may be less than what is specified by
the USB specification.
Work around
None.
Affected Silicon Revisions
A0
A0
A0
A0
X
X
X
X
PIC32MX575/675/695/775/795
22. Module: WDT
23. Module: Oscillator
24. Module: Oscillator
When code-protect is enabled, the WDT is not
held in reset during the POR RAM Clear Sequence
(RCS). If the WDT period does not exceed the
RCS period, the WDT will reset the part and the
RCS sequence will restart.
Work around
Use WDT periods equal to or longer than 128 ms.
Since the RCS and WDT run concurrently,
firmware will have a reduced period in which to
service the WDT for the first time.
Affected Silicon Revisions
Clock switching and Two-Speed Start-up may
cause a general exception when the reserved bit 8
of the DDPCON register is ‘0’.
Work around
Ensure that the reserved bit 8 of the DDPCON
register to set to ‘1’. For example,
Affected Silicon Revisions
Clock source switching may cause a general
exception or POR when switching from a slow
clock to a fast clock.
Work around
Clock source switches should be performed by
first switching to the FRC, and then switching to
the target clock source.
Affected Silicon Revisions
A0
A0
A0
Note:
X
X
X
DDPCON |= 0x100;
If the peripheral library is being used,
clock
automatically through the FRC.
switching
DS80480E-page 7
is
performed