AT89C51CC03UA-RDTUM Atmel, AT89C51CC03UA-RDTUM Datasheet - Page 36
![IC 8051 MCU FLASH 64K 64-VQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT89C51CC03UA-RDTUM
Manufacturer Part Number
AT89C51CC03UA-RDTUM
Description
IC 8051 MCU FLASH 64K 64-VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheet
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
Specifications of AT89C51CC03UA-RDTUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
2
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64VQFP
Device Core
8051
Family Name
AT89
Maximum Speed
60 MHz
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Quantity
Price
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Registers
36
AT89C51CC03
Table 10. PCON Register
PCON (S87:h) Power configuration Register
Reset Value= XXXX 0000b
Number
Bit
7-4
7
-
3
2
1
0
Mnemonic Description
GF1
GF0
Bit
IDL
PD
6
-
-
Reserved
The value read from these bits is indeterminate. Do not set these bits.
General Purpose flag 1
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
General Purpose flag 0
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
Power-Down Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-Down mode.
If IDL and PD are both set, PD takes precedence.
Idle Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes precedence.
5
-
4
-
GF1
3
GF0
2
4182O–CAN–09/08
PD
1
IDL
0
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