PIC17C752-33E/L Microchip Technology, PIC17C752-33E/L Datasheet - Page 167

• Manufacturer Part Number: PIC17C752-33E/L
• Description: IC MCU CMOS 33MHZ 8K EPRM 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C752-33E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 68-PLCC
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 678 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DM173001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.2.14
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/
transmit the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to ‘0’. When the baud rate generator times
out, the SCL pin will be brought high and one T
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT<4>) is set. A
T
set (Figure 15-31).
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a STOP bit is detected (i.e., bus is free).
FIGURE 15-31:
BRG
2000 Microchip Technology Inc.
later, the PEN bit is cleared and the SSPIF bit is
STOP CONDITION TIMING
SCL
SDA
Write to SSPCON2
Falling Edge of
9th Clock
Note: T
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
Set PEN
BRG
= one baud rate generator period.
SDA asserted low before rising edge of clock
to setup STOP condition.
T
T
BRG
BRG
BRG
T
SCL brought high after T
BRG
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
P
T
BRG
15.2.14.1
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
BRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set.
, followed by SDA = 1 for T
BRG
.
WCOL Status Flag
PIC17C7XX
BRG
DS30289B-page 167