PIC17C756A-33E/L Microchip Technology, PIC17C756A-33E/L Datasheet - Page 125
![IC MCU CMOS 33MHZ 16K EPRM68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC17C756A-33E/L
Manufacturer Part Number
PIC17C756A-33E/L
Description
IC MCU CMOS 33MHZ 16K EPRM68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A-33E/L
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
68-PLCC
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
50
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C756A-33E/L
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC17C756A-33E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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14.2.2
The receiver block diagram is shown in Figure 14-2.
The data comes in the RX/DT pin and drives the data
recovery block. The data recovery block is actually a
high speed shifter operating at 16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG (if it is
empty). If the transfer is complete, the interrupt bit,
RCIF, is set. The actual interrupt can be enabled/
disabled by setting/clearing the RCIE bit. RCIF is a
read only bit which is cleared by the hardware. It is
cleared when RCREG has been read and is empty.
RCREG is a double buffered register (i.e., it is a two-
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte begin shifting to the RSR. On detection of the
STOP bit of the third byte, if the RCREG is still full, then
the overrun error bit, OERR (RCSTA<1>) will be set.
The word in the RSR will be lost. RCREG can be read
twice to retrieve the two bytes in the FIFO. The OERR
bit has to be cleared in software which is done by reset-
FIGURE 14-5:
FIGURE 14-6:
2000 Microchip Technology Inc.
(RX/DT pin)
Baud CLK
x16 CLK
USART ASYNCHRONOUS
RECEIVER
OSC
RX
.
Q2, Q4 CLK
RX PIN SAMPLING SCHEME
START BIT DETECT
(RX/DT pin)
x16 CLK
1
RX
2
3
RX sampled low
4
5
6
First rising edge of x16 clock after RX pin goes low
7
Samples
8
START bit
ting the receive logic (CREN is set). If the OERR bit is
set, transfers from the RSR to RCREG are inhibited, so
it is essential to clear the OERR bit if it is set. The fram-
ing error bit FERR (RCSTA<2>) is set if a STOP bit is
not detected.
14.2.3
The data on the RX/DT pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX/DT pin. The sampling is done
on the seventh, eighth and ninth falling edges of a x16
clock (Figure 14-5).
The x16 clock is a free running clock and the three
sample points occur at a frequency of every 16 falling
edges.
9
Note:
10
Baud CLK for all but START bit
11
The FERR and the 9th receive bit are buff-
ered the same way as the receive data.
Reading the RCREG register will allow the
RX9D and FERR bits to be loaded with val-
ues for the next received data. Therefore,
it is essential for the user to read the
RCSTA register before reading RCREG, in
order not to lose the old FERR and RX9D
information.
SAMPLING
START bit
12
13
14
PIC17C7XX
15
16
DS30289B-page 125
1
Bit0
2
3
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