PIC17C756A-33E/L Microchip Technology, PIC17C756A-33E/L Datasheet - Page 46
![IC MCU CMOS 33MHZ 16K EPRM68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC17C756A-33E/L
Manufacturer Part Number
PIC17C756A-33E/L
Description
IC MCU CMOS 33MHZ 16K EPRM68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A-33E/L
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
68-PLCC
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
50
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C756A-33E/L
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC17C756A-33E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C7XX
7.2
Data memory is partitioned into two areas. The first is
the General Purpose Registers (GPR) area, and the
second is the Special Function Registers (SFR) area.
The SFRs control and provide status of device opera-
tion.
Portions of data memory are banked, this occurs in
both areas. The GPR area is banked to allow greater
than 232 bytes of general purpose RAM.
Banking requires the use of control bits for bank selec-
tion. These control bits are located in the Bank Select
Register (BSR). If an access is made to the unbanked
region, the BSR bits are ignored. Figure 7-5 shows the
data memory map organization.
Instructions MOVPF and MOVFP provide the means to
move values from the peripheral area (“P”) to any loca-
tion in the register file (“F”), and vice-versa. The defini-
tion of the “P” range is from 0h to 1Fh, while the “F”
range is 0h to FFh. The “P” range has six more loca-
tions than peripheral registers, which can be used as
General Purpose Registers. This can be useful in some
applications where variables need to be copied to other
locations in the general purpose RAM (such as saving
status information during an interrupt).
The entire data memory can be accessed either
directly, or indirectly (through file select registers FSR0
and FSR1) (see Section 7.4). Indirect addressing uses
the appropriate control bits of the BSR for access into
the banked areas of data memory. The BSR is
explained in greater detail in Section 7.8.
DS30289B-page 46
Data Memory Organization
7.2.1
All devices have some amount of GPR area. The GPRs
are 8-bits wide. When the GPR area is greater than
232, it must be banked to allow access to the additional
memory space.
All the PIC17C7XX devices have banked memory in
the GPR area. To facilitate switching between these
banks, the MOVLR bank instruction has been added to
the instruction set. GPRs are not initialized by a Power-
on Reset and are unchanged on all other RESETS.
7.2.2
The SFRs are used by the CPU and peripheral func-
tions to control the operation of the device (Figure 7-5).
These registers are static RAM.
The SFRs can be classified into two sets, those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described here, while those related to a
peripheral feature are described in the section for each
peripheral feature.
The peripheral registers are in the banked portion of
memory, while the core registers are in the unbanked
region. To facilitate switching between the peripheral
banks, the MOVLB bank instruction has been provided.
GENERAL PURPOSE REGISTER
(GPR)
SPECIAL FUNCTION REGISTERS
(SFR)
2000 Microchip Technology Inc.
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