ATMEGA1281-16MU Atmel, ATMEGA1281-16MU Datasheet - Page 296

• Manufacturer Part Number: ATMEGA1281-16MU
• Description: IC MCU AVR 128K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1281-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 6
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRDB101 - MODULE DISPLAY LCD/RGB BACKLIGHT770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26. JTAG Interface and On-chip Debug System
26.1
26.2
2549M–AVR–09/10
Features
Overview
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The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
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A brief description is given in the following sections. Detailed descriptions for Programming via
the JTAG interface, and using the Boundary-scan Chain can be found in the sections
ming via the JTAG Interface” on page 354
302, respectively. The On-chip Debug support is considered being private JTAG instructions,
and distributed within ATMEL and to selected third party vendors only.
Figure 26-1 on page 297
system. The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP
Controller selects either the JTAG Instruction Register or one of several Data Registers as the
scan chain (Shift Register) between the TDI – input and TDO – output. The Instruction Register
holds JTAG instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used
for board-level testing. The JTAG Programming Interface (actually consisting of several physical
and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal
Scan Chain and Break Point Scan Chain are used for On-chip debugging only.
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
Debugger Access to:
Extensive On-chip Debug Support for Break Conditions, Including
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
On-chip Debugging Supported by AVR Studio
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
– Program Counter
– EEPROM and Flash Memories
– AVR Break Instruction
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Break Points on Single Address or Address Range
– Data Memory Break Points on Single Address or Address Range
Testing PCBs by using the JTAG Boundary-scan capability.
Programming the non-volatile memories, Fuses and Lock bits.
On-chip debugging.
shows a block diagram of the JTAG interface and the On-chip Debug
ATmega640/1280/1281/2560/2561
and
®
“IEEE 1149.1 (JTAG) Boundary-scan” on page
“Program-
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