ATMEGA1281-16MU Atmel, ATMEGA1281-16MU Datasheet - Page 381

• Manufacturer Part Number: ATMEGA1281-16MU
• Description: IC MCU AVR 128K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1281-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 6
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRDB101 - MODULE DISPLAY LCD/RGB BACKLIGHT770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 30-15. External Data Memory Characteristics, 2.7 to 5.5 Volts, SRWn1 = 1, SRWn0 = 0
Table 30-16. External Data Memory Characteristics, 2.7 to 5.5 Volts, SRWn1 = 1, SRWn0 = 1
2549M–AVR–09/10
0
10
12
15
16
0
10
12
14
15
16
Symbol
1/t
t
t
t
t
Symbol
1/t
t
t
t
t
t
RLDV
RLRH
DVWH
WLWH
RLDV
RLRH
WHDX
DVWH
WLWH
CLCL
CLCL
Parameter
Oscillator Frequency
Read Low to Data Valid
RD Pulse Width
Data Valid to WR High
WR Pulse Width
Parameter
Oscillator Frequency
Read Low to Data Valid
RD Pulse Width
Data Hold After WR High
Data Valid to WR High
WR Pulse Width
Figure 30-9. External Memory Timing (SRWn1 = 0, SRWn0 = 0
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0
A15:8
CPU
ALE
WR
RD
)
Prev. addr.
Prev. data
Min
735
750
735
Min
735
485
750
735
4 MHz Oscillator
4 MHz Oscillator
ATmega640/1280/1281/2560/2561
T1
1
Address
Address
4
2
Max
Max
690
690
5
T2
6
3a
3b
XX
7
8
13
10
3.0t
3.0t
3.0t
2.0t
3.0t
Address
3.0t
3.0t
T3
15
Min
Min
CLCL
CLCL
CLCL
CLCL
CLCL
0.0
0.0
12
Data
Data
16
Variable Oscillator
Variable Oscillator
CLCL
CLCL
9
-15
-15
-15
-15
-15
11
3.0t
3.0t
T4
14
Max
Max
CLCL
CLCL
8
8
-60
-60
MHz
MHz
Unit
Unit
ns
ns
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