DSPIC30F6011A-30I/PF Microchip Technology, DSPIC30F6011A-30I/PF Datasheet
DSPIC30F6011A-30I/PF
Specifications of DSPIC30F6011A-30I/PF
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DSPIC30F6011A-30I/PF Summary of contents
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... Rev. B0 Silicon Errata The dsPIC30F6011A/6012A/6013A/6014A (Rev. B0) samples that you have received were found to conform to the specifications and functionality described in the following documents: • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70143 – “dsPIC30F6011A/6012A/6013A/6014A Data Sheet” • DS70046 – “dsPIC30F Family Reference Manual” ...
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... PLL Lock Status Bit The PLL LOCK Status bit (OSCCON<5>) can occasionally get cleared and generate an oscillator failure trap even when the PLL is still locked and functioning correctly. 9. PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of any PSV page ...
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... Module: Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet. Work arounds To avoid this issue, any of the following three work arounds can be implemented, depending on the application requirements ...
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... Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 512 kHz Low-Power RC (LPRC) Oscillator with a 64:1 postscaler mode. This enables the device to operate at 0.002 MIPS, thereby significantly reducing consumption of the device. Similarly, instead of using an interrupt to wake-up the device from ...
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... Module When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... Module there are two I C devices on the bus, one of them is acting as the Master receiver and the other as the Slave transmitter. If both devices are config- ured for 10-bit addressing mode, and have the same value in the A10 and A9 bits of their ...
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... Module When the I C module is enabled by setting the I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates “Communication 2 Start” to all devices on the I C bus, and can cause a bus collision in a multi-master configuration ...
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... APPENDIX A: REVISION HISTORY Revision A (2/2007) Original version of this document. Revision B (9/2007) Added silicon issue 3 (Sleep Mode). Revision C (12/2007) 2 Added silicon issues 4 and 5 (I C), and 6 (I/O Port – Port Pin Multiplexed with IC1). Revision D (5/2008) 2 Added silicon issues 7 and 8 (I C), and 9 (Timer). ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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