DSPIC30F6011A-30I/PF Microchip Technology, DSPIC30F6011A-30I/PF Datasheet
DSPIC30F6011A-30I/PF
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DSPIC30F6011A-30I/PF Summary of contents
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... Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the dsPIC30F6011A/6012A/6013A/ 6014A silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current ...
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... TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number CPU 1. DAW.b Instruction Output PWM Mode 2. Compare Sleep — 3. Mode 2 I C™ Slave Mode 4. I/O Port Pin 5. Multiplexed with IC1 10-bit 6. Addressing Timer Sleep Mode 7. PLL Lock Status 8. bit PSV — 9. Operations ...
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... Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2010 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A Issue Summary For this revision of silicon, the LP Oscillator is not operational. ADC event triggers from the INT0 pin will not wake-up the device from Sleep mode if the SMPI bits are non-zero ...
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... Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B1). 1. Module: CPU The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR< ...
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... NOP .endr ; Place SLEEP instruction in the last word of program memory PWRSAV #0 © 2010 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A This can be accomplished by replacing all occurrences of the PWRSAV #0 instruction with a function call to a suitably aligned subroutine. The address( ) attribute provided by the MPLAB ASM30 assembler can be utilized to correctly align the instructions in the subroutine ...
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... Work around 2: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 512 kHz Low-Power RC (LPRC) Oscillator with a 64:1 postscaler mode. This enables the device to operate at 0.002 MIPS, thereby significantly reducing consumption of the device. Similarly, instead of ...
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... Clear the I C receiver interrupt flag SI2CF back to step 1 to continue receiving incoming data bytes. © 2010 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A Work around 2: Use this work around for applications in which the receiver interrupt is required. Assuming that the RBF and the I2COV flags in the I2CSTAT ...
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... Module there are two I C devices on the bus, one of them is acting as the Master receiver and the other as the Slave transmitter. If both devices are config- ured for 10-bit addressing mode, and have the same value in the A10 and A9 bits of their ...
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... None. Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A 12. Module: I When the I I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates “Communication Start” to all devices on the I with the a bus collision in a multi-master configuration ...
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... Module: CAN CAN Receive filters 3, 4 and 5 may not work for a given combination of instruction cycle speed and CAN bit time quanta. Work around Do not use CAN RX filters 3, 4 and 5. Instead, use filters 0, 1 and 2. Affected Silicon Revisions 14. Module: CPU Sequential MAC class instructions, which prefetch data from Y data space using ± ...
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... Module: OSC2 Pin Table 20-2 (see below) from the “dsPIC30F6011A/ 6012A/6013A/6014A Data Sheet” (DS70143A) lists the device clock operational modes. The data in the table is correct with the following exceptions: • Digital I/O functionality is not operational in the FRC with PLL (4x, 8x and 16x PLL) Oscillator mode. • ...
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... Module: LP Oscillator The 32 kHz LP Oscillator module is not operational for this version of silicon. Work around None. Affected Silicon Revisions 19. Module: ADC ADC event triggers from the INT0 pin will not wake-up the device from Sleep mode if the SMPI bits are non-zero. This means that if the ADC is ...
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... Symbol Characteristic No. V Input Low Voltage IL DI19 SDA, SCL V Input High Voltage IH DI29 SDA, SCL © 2010 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A specifica- IL Standard Operating Conditions: 3.3V and 5.0V (±10%) (unless otherwise stated) Operating temperature Min Typ Max V — 0.8 SS 2.1 — ...
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... This document replaces the following errata documents: • DS80242, “dsPIC30F6011A/6012A/6013A/6014A Rev. A2 Silicon Errata” • DS80303, “dsPIC30F6011A/6012A/6013A/6014A Rev. B0 Silicon Errata” • DS80401, “dsPIC30F6011A/6012A/6013A/6014A Rev. B1 Silicon Errata” Rev B Document (6/2010) Added silicon issue 21 (ADC) and data sheet clarification 1 (DC Characteristics: I/O Pin Input Specifications). ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2010 Microchip Technology Inc. 01/05/10 ...