ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 60
![MCU AVR 256KB FLASH A3B 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
8116I–AVR–09/10
Mnemonics
LD
LDD
LD
LD
LD
LDD
STS
ST
ST
ST
ST
ST
ST
STD
ST
ST
ST
STD
LPM
LPM
LPM
ELPM
ELPM
ELPM
SPM
SPM
IN
OUT
PUSH
POP
LSL
LSR
Operands
Rd, -Y
Rd, Y+q
Rd, Z
Rd, Z+
Rd, -Z
Rd, Z+q
k, Rr
X, Rr
X+, Rr
-X, Rr
Y, Rr
Y+, Rr
-Y, Rr
Y+q, Rr
Z, Rr
Z+, Rr
-Z, Rr
Z+q,Rr
Rd, Z
Rd, Z+
Rd, Z
Rd, Z+
Z+
Rd, A
A, Rr
Rr
Rd
Rd
Rd
Description
Load Indirect and Pre-Decrement
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Load Indirect with Displacement
Store Direct to Data Space
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Load Program Memory
Load Program Memory
Load Program Memory and Post-Increment
Extended Load Program Memory
Extended Load Program Memory
Extended Load Program Memory and Post-
Increment
Store Program Memory
Store Program Memory and Post-Increment
by 2
In From I/O Location
Out To I/O Location
Push Register on Stack
Pop Register from Stack
Logical Shift Left
Logical Shift Right
Bit and Bit-test Instructions
(RAMPZ:Z)
(RAMPZ:Z)
Rd(n+1)
STACK
(Y + q)
(Z + q)
I/O(A)
Rd(0)
Rd(n)
Rd(7)
Operation
(X)
(X)
(X)
(Y)
(Y)
(Y)
Rd
Rd
Rd
Rd
Rd
Rd
(Z)
(Z)
R0
Rd
Rd
R0
Rd
Rd
Rd
Rd
(k)
C
C
Y
Z
Z
X
X
Y
Y
Z
Z
Z
Z
Z
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Y - 1
(Y)
(Y + q)
(Z)
(Z),
Z+1
Z - 1,
(Z)
(Z + q)
Rd
Rr
Rr,
X + 1
X - 1,
Rr
Rr
Rr,
Y + 1
Y - 1,
Rr
Rr
Rr
Rr
Z + 1
Z - 1
Rr
(Z)
(Z)
(Z),
Z + 1
(RAMPZ:Z)
(RAMPZ:Z)
(RAMPZ:Z),
Z + 1
R1:R0
R1:R0,
Z + 2
I/O(A)
Rr
Rr
STACK
Rd(n),
0,
Rd(7)
Rd(n+1),
0,
Rd(0)
XMEGA A3B
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,C,N,V,H
Z,C,N,V
#Clocks
2
2
1
1
2
2
2
1
1
2
1
1
2
2
1
1
2
2
1
2
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
(1)(2)
3
3
3
3
3
3
1
1
1
1
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
-
-
(1)
(1)
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