ATSAM3U2EA-CU Atmel, ATSAM3U2EA-CU Datasheet - Page 958

• Manufacturer Part Number: ATSAM3U2EA-CU
• Description: IC MCU 32BIT 128KB FLSH 144LFBGA
• Manufacturer: Atmel
• Series: SAM3Ur

Specifications of ATSAM3U2EA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b, 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 36 KB
• Interface Type: 4xUSART, 2xTWI, 5xSPI, Bus
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 8
• Operating Supply Voltage: 1.62 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3U-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 39-11. Autovalid with DMA
Note:
39.6.8.7
39.6.8.8
958
958
In the illustration above Autovalid validates a bank as full, although this might not be the case, in order to continue processing
data and to send to DMA.
SAM3U Series
SAM3U Series
Bank (system)
Write
Bank (usb)
Virtual TX_PK_RDY Bank 0
Virtual TX_PK_RDY Bank 1
TX_PK_RDY
(Virtual 0 & Virtual 1)
Isochronous IN
High Bandwidth Isochronous Endpoint Handling: IN Example
Bank 1
Bank 0
write bank 0
Bank 0
Isochronous-IN is used to transmit a stream of data whose timing is implied by the delivery rate.
Isochronous transfer provides periodic, continuous communication between host and device.
It guarantees bandwidth and low latencies appropriate for telephony, audio, video, etc.
If the endpoint is not available (TX_PK_RDY = 0), then the device does not answer to the host.
An ERR_FL_ISO interrupt is generated in the UDPHS_EPTSTAx register and once enabled,
then sent to the CPU.
The STALL_SNT command bit is not used for an ISO-IN endpoint.
For high bandwidth isochronous endpoints, the DMA can be programmed with the number of
transactions (BUFF_LENGTH field in UDPHS_DMACONTROLx) and the system should provide
the required number of packets per microframe, otherwise, the host will notice a sequencing
problem.
bank 0 is full
write bank 1
Bank 1
Bank 0
bank 1 is full
IN data 0
Bank 0
write bank 0
bank 0 is full
Bank 1
IN data 1
Bank 1
Bank 0
IN data 0
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Bank 1