DSPIC30F6013T-20E/PF Microchip Technology, DSPIC30F6013T-20E/PF Datasheet - Page 20
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DSPIC30F6013T-20E/PF
Manufacturer Part Number
DSPIC30F6013T-20E/PF
Description
IC DSPIC MCU/DSP 132K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F6014-20IPF.pdf
(228 pages)
2.DSPIC30F6014-20IPF.pdf
(22 pages)
3.DSPIC30F6014-20IPF.pdf
(28 pages)
Specifications of DSPIC30F6013T-20E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F6013T20EP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6013T-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
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dsPIC30F6011/6012/6013/6014
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The fol-
lowing instructions and data sizes are supported:
1.
2.
3.
4.
5.
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
DS70117F-page 18
DIVF
DIV.sd
DIV.ud
DIV.sw
DIV.uw
DIVF - 16/16 signed fractional divide
DIV.sd - 32/16 signed divide
DIV.ud - 32/16 unsigned divide
DIV.sw - 16/16 signed divide
DIV.uw - 16/16 unsigned divide
Instruction
Divide Support
DIVIDE INSTRUCTIONS
Signed fractional divide: Wm/Wn
Signed divide: (Wm + 1:Wm)/Wn
Unsigned divide: (Wm + 1:Wm/Wn
Signed divide: Wm/Wn
Unsigned divide: Wm/Wn
W0; Rem
W0; Rem
W0; Rem
W0; Rem
W0; Rem
W1
W1
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruc-
tion as shown in Table 2-1 (REPEAT will execute the tar-
get instruction {operand value + 1} times). The REPEAT
loop count must be setup for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
Function
Note:
W1
W1
W
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
© 2006 Microchip Technology Inc.
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