DSPIC30F6010T-20E/PF Microchip Technology, DSPIC30F6010T-20E/PF Datasheet - Page 114
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
DSPIC30F6010T-20E/PF
Manufacturer Part Number
DSPIC30F6010T-20E/PF
Description
IC PSPIC MCU/DSP 144K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F6010A-30IPF.pdf
(22 pages)
3.DSPIC30F6010-20IPF.pdf
(222 pages)
4.DSPIC30F6010-20IPF.pdf
(30 pages)
Specifications of DSPIC30F6010T-20E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F6010T20EP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6010T-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F6010A-30IPF PDF datasheet #2
- DSPIC30F6010-20IPF PDF datasheet #3
- DSPIC30F6010-20IPF PDF datasheet #4
- Current page: 114 of 222
- Download datasheet (4Mb)
dsPIC30F6010
18.10 UART Operation During CPU
18.10.1
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’. If
entry into Sleep mode occurs while a transmission is
in progress, then the transmission is aborted. The
UxTX pin is driven to logic ‘1’. Similarly, if entry into
Sleep mode occurs while a reception is in progress,
then the reception is aborted. The UxSTA, UxMODE,
transmit and receive registers and buffers, and the
UxBRG register are not affected by Sleep mode.
If the WAKE bit (UxMODE<7>) is set before the device
enters Sleep mode, then a falling edge on the UxRX
pin will generate a receive interrupt. The Receive
Interrupt Select Mode bit (URXISEL) has no effect for
this function. If the receive interrupt is enabled, then
this will wake-up the device from Sleep. The UARTEN
bit must be set in order to generate a wake-up
interrupt.
DS70119E-page 112
Sleep and Idle Modes
UART OPERATION DURING CPU
SLEEP MODE
18.10.2
For the UART, the USIDL bit selects if the module will
stop operation when the device enters Idle mode, or
whether the module will continue on Idle. If USIDL = 0,
the module will continue operation during Idle mode. If
USIDL = 1, the module will stop on Idle.
UART OPERATION DURING CPU
IDLE MODE
© 2006 Microchip Technology Inc.
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