DSPIC30F6010-30I/PF Microchip Technology, DSPIC30F6010-30I/PF Datasheet
DSPIC30F6010-30I/PF
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DSPIC30F6010-30I/PF Summary of contents
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... Rev. B2 Silicon Errata The dsPIC30F6010 (Rev. B2) samples that you have received were found to conform to the specifications and functionality described in the following documents: • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70119 – “dsPIC30F6010 Data Sheet” • DS70046 – “dsPIC30F Family Reference Manual” ...
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... DISI Instruction The DISI instruction will not disable interrupts if a DISI instruction is executed in the same instruction cycle that the decrements to zero. 11. 32-bit General Purpose Timers The 32-bit general purpose timers do not function as specified for prescaler ratios other than 1:1. 12. Output Compare Module in PWM Mode Output compare will produce a glitch when loading 0% duty cycle in PWM mode ...
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... The following sections describe the errata and work around to these errata, where they may apply. © 2008 Microchip Technology Inc. dsPIC30F6010 1. Module: Data EEPROM – Speed At device throughput is greater than 20 MIPS for V in the range 4.75V to 5.5V (or 10 MIPS for ...
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... Module: MAC Class Instructions with ±4 Address Modification Sequential MAC class instructions, which prefetch data from Y data space using ±4 address modification, will cause an address error trap. The trap occurs only when all of the following conditions are true: 1. Two sequential MAC class instructions (or a MAC class instruction executed in a REPEAT or DO loop) that prefetch from Y data space ...
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... Table 1 is fetched from program memory using PSV, the STATUS register, SR and/or the results may be corrupted. These instructions are identified in Table 1. Example 2 demonstrates one scenario where this occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F6010 devices. TABLE 1: AFFECTED INSTRUCTIONS (1) Instruction ADDC ...
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... Module: Early Termination of Nested DO Loops When using two DO loops in a nested fashion, terminating the inner-level DO loop by setting the EDT(CORCON<11>) bit will produce unexpected results. Specifically, the device may continue executing code within the outer DO loop forever. This erratum does not affect the operation of the MPLAB C30 compiler ...
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... RETFIE 2. Immediately prior to executing the RETFIE instruction, increase the CPU priority level by modifying the IPL<2:0> (SR<7:5>) bits to ‘111’ as shown in Example 9. This will disable all interrupts between priority levels 1 through 7. dsPIC30F6010 nesting is enabled (or DISI BEFORE RETFIE ;Timer1 ISR ;This line optional ...
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... EXAMPLE 9: RAISE IPL BEFORE RETFIE __T1Interrupt: ;Timer1 ISR PUSH W0 ....... BCLR IFS0, #T1IF MOV.B #0xE0, W0 MOV.B WREG, SR POP W0 RETFIE ;Another interrupt occurs ;here and it is processed ;correctly 10. Module: DISI Instruction When a user executes a DISI #7, for example, this will disable interrupts for cycles (7 + the DISI instruction itself) ...
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... Output” columns in Table 2. Work around None. Observed Output PWM Low Low Output on PWM1L pin is shortened by dead time Low Low Low Output on PWM1H pin is shortened by dead time dsPIC30F6010 Time Base Prescaler Override (1,2,3) Comments DS80195H-page 9 ...
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... Module: Motor Control PWM – Output Override Synchronization Unexpected results may occur when the PWM pins are manually controlled using the OVDCON register and the OSYNC bit (PWMCON2<1>) is set. Work around Set OSYNC = 0 when the PWM pins are manually controlled using the OVDCON register. ...
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... Range Temp Range DD (in volts) (in °C) 4.75 to 5.5 -40 to +85 4.75 to 5.5 -40 to +125 Note 1: Applications that use the CAN peripherals and Data EEPROM should also refer to Errata 1. and 21. © 2008 Microchip Technology Inc. dsPIC30F6010 ) (1) Max MIPS dsPIC30FXXX-30I dsPIC30FXXX-20I 30 20 — — ...
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... Module: 4x PLL Operation When the 4x PLL mode of operation is selected, the specified input frequency range of 4-10 MHz is not fully supported. When device V is 2.5-3.0V, the 4x PLL input DD frequency must be in the range of 4-5 MHz. When device V is 3.0-3.6V, the 4x PLL input frequency ...
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... The CAN module does not cause a filter match with filters 3, 4 and baud rate of more than 500 kbps. Work around Use only filters 0, 1 and 2 with a baud rate of more than 500 kbps. // Instead of 0xFFFF // Clear QEI interrupt flag // x=2 for dsPIC30F // x=3 for dsPIC33F dsPIC30F6010 DS80195H-page 13 ...
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... GotoSleep( ) function call. This ensures that the device continues executing the correct code sequence after waking up from Sleep mode. Example 15 demonstrates the work around described above would apply to a dsPIC30F6010 device. ; Ensure flag is reset ; Return from Interrupt Service Routine the function ...
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... Manual” (DS70046) for more details on performing a clock switch operation. Note: The above work around is recommended for users for whom application hardware changes are possible, and also for users whose includes a 32 kHz LP Oscillator crystal. dsPIC30F6010 or Section 29. “Oscillator” application hardware already ...
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... Module Module 2 When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... Status bit (OSCCON<3>). If this bit is clear, return from the trap service routine immediately and continue program execution. © 2008 Microchip Technology Inc. dsPIC30F6010 36. Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page. This only occurs when using the following addressing modes: • ...
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... Module When the I C module is enabled by setting the I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates “Communication 2 Start” to all devices on the I C bus, and can cause a bus collision in a multi-master configuration ...
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... Port – Port Pin Multiplexed with IC1). Revision G (5/2008) 2 Added silicon issues 34 and 35 (I C), and 36 (Timer). Revision H (9/2008) 2 Replaced issues 30 and with issue 39 (I Added silicon issues 35 (PLL Lock Status Bit), 36 (PSV 2 Operations) and 37-39 (I C). © 2008 Microchip Technology Inc. 2 C), 32 (Motor 2 C). dsPIC30F6010 DS80195H-page 19 ...
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... NOTES: DS80195H-page 20 © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...