P89LPC922A1FDH,112 NXP Semiconductors, P89LPC922A1FDH,112 Datasheet - Page 41

IC 80C51 MCU FLASH 8K 20-TSSOP

P89LPC922A1FDH,112

Manufacturer Part Number
P89LPC922A1FDH,112
Description
IC 80C51 MCU FLASH 8K 20-TSSOP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet

Specifications of P89LPC922A1FDH,112

Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
20-TSSOP
Core Processor
8051
Core Size
8-Bit
Speed
18MHz
Connectivity
I²C, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
P89LPC
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
15
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
935288637112
NXP Semiconductors
P89LPC92X1
Product data sheet
Fig 13. Comparator input and output connections
(P0.5) CMPREF
7.24.1 Internal reference voltage
7.24.2 Comparator interrupt
7.24.3 Comparators and power reduction modes
(P0.4) CIN1A
(P0.3) CIN1B
(P0.2) CIN2A
(P0.1) CIN2B
V
ref(bg)
The overall connections to both comparators are shown in
function to V
When each comparator is first enabled, the comparator output and interrupt flag are not
guaranteed to be stable for 10 μs. The corresponding comparator interrupt should not be
enabled during that time, and the comparator interrupt flag must be cleared before the
interrupt is enabled in order to prevent an immediate interrupt service.
When a comparator is disabled the comparator’s output, COn, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator flag, CMFn. This will
cause an interrupt if the comparator interrupt is enabled. The user should therefore
disable the comparator interrupt prior to disabling the comparator. Additionally, the user
should clear the comparator flag, CMFn, after disabling the comparator.
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to as
V
Each comparator has an interrupt flag contained in its configuration register. This flag is
set whenever the comparator output changes state. The flag may be polled by software or
may be used to generate an interrupt. The two comparators use one common interrupt
vector. If both comparators enable interrupts, after entering the interrupt service routine,
the user needs to read the flags to determine which comparator caused the interrupt.
Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down mode.
ref(bg)
, is 1.23 V ± 10 %.
DD
CN1
CN2
CP1
CP2
= 2.4 V.
All information provided in this document is subject to legal disclaimers.
comparator 1
comparator 2
Rev. 2 — 1 December 2010
P89LPC9201/9211/922A1/9241/
CO1
CO2
change detect
change detect
OE1
OE2
CMF1
CMF2
8-bit microcontroller with 8-bit ADC
CMP1 (P0.6)
CMP2 (P0.0)
Figure
EC
13. The comparators
002aae433
interrupt
© NXP B.V. 2010. All rights reserved.
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