P89LPC972FDH,129 NXP Semiconductors, P89LPC972FDH,129 Datasheet - Page 7

MCU 80C51 8KB FLASH 20TSSOP

P89LPC972FDH,129

Manufacturer Part Number
P89LPC972FDH,129
Description
MCU 80C51 8KB FLASH 20TSSOP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet

Specifications of P89LPC972FDH,129

Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
20-TSSOP
Core Processor
8051
Core Size
8-Bit
Speed
18MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
P89LPC
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
15
Number Of Timers
5
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
935290299129
NXP Semiconductors
Table 3.
P89LPC97X
Product data sheet
Symbol
P0.0 to P0.7
P0.0/CMP2/KBI0/
SPICLK
P0.1/CIN2B/
KBI1
P0.2/CIN2A/
KBI2
P0.3/CIN1B/
KBI3/T2
P0.4/CIN1A/
KBI4
P0.5/CMPREF/
KBI5/T3
Pin description
6.2 Pin description
Pin
DIP20,
TSSOP20
1
20
19
18
17
16
Type Description
I/O
I/O
O
I
I/O
I/O
I
I
I/O
I
I
I/O
I
I
I/O
I/O
I
I
I/O
I
I
I/O
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input-only mode with the internal pull-up
disabled. The operation of Port 0 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to
7.16.1 “Port configurations”
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt trigger inputs.
Port 0 also provides various special functions as described below:
P0.0 — Port 0 bit 0.
CMP2 — Comparator 2 output
KBI0 — Keyboard input 0.
SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input (pin remap).
P0.1 — Port 0 bit 1.
CIN2B — Comparator 2 positive input B.
KBI1 — Keyboard input 1.
P0.2 — Port 0 bit 2.
CIN2A — Comparator 2 positive input A.
KBI2 — Keyboard input 2.
P0.3 — Port 0 bit 3. High current source.
CIN1B — Comparator 1 positive input B.
KBI3 — Keyboard input 3.
T2 — Timer/counter 2 external count input or overflow output.
P0.4 — Port 0 bit 4. High current source.
CIN1A — Comparator 1 positive input A.
KBI4 — Keyboard input 4.
P0.5 — Port 0 bit 5. High current source.
CMPREF — Comparator reference (negative) input.
KBI5 — Keyboard input 5.
T3 — Timer/counter 3 external count input or overflow output.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 8 June 2010
8-bit microcontroller with accelerated two-clock 80C51 core
and
Table 11 “Static characteristics”
P89LPC970/971/972
© NXP B.V. 2010. All rights reserved.
for details.
Section
7 of 66

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