P80C32SBBB,557 NXP Semiconductors, P80C32SBBB,557 Datasheet - Page 18

• Manufacturer Part Number: P80C32SBBB,557
• Description: IC 80C51 MCU 256 ROMLESS 44-QFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C32SBBB,557

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-MQFP, 44-PQFP
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 935255820557; P80C32SBBB; P80C32SBBB

Philips Semiconductors
2000 Aug 07
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
BIT
IPH.7
IPH.6
IPH.5
IPH.4
IPH.3
IPH.2
IPH.1
IPH.0
IPH (B7H)
IP (0B8H)
SYMBOL
—
—
PT2
PS
PT1
PX1
PT0
PX0
SYMBOL
—
—
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit high.
Serial Port interrupt priority bit high.
Timer 1 interrupt priority bit high.
External interrupt 1 priority bit high.
Timer 0 interrupt priority bit high.
External interrupt 0 priority bit high.
—
—
7
7
—
—
6
6
PT2H
PT2
5
5
Figure 12. IPH Registers
Figure 11. IP Registers
PSH
PS
4
4
18
PT1H
PT1
3
3
PX1H
PX1
2
2
PT0H
PT0
1
1
SU00572
PX0H
PX0
0
0
SU01058
80C31/80C32
Product specification