P80C552EFA/08,512 NXP Semiconductors, P80C552EFA/08,512 Datasheet - Page 17

• Manufacturer Part Number: P80C552EFA/08,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C552EFA/08,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 256Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Package: 68PLCC
• Family Name: 80C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1237-5; 935237080512; P80C552EFA

Philips Semiconductors
2002 Sep 03
WRITE TO SBUF
INSTRUCTION
PORT 0
PORT 2
INPUT DATA
OUTPUT DATA
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
CLEAR RI
PSEN
ALE
WR
CLOCK
ALE
t
AVLL
0
t
QVXH
FROM RI OR DPL
0.8 V
A0–A7
V
t
IH1
1
LLAX
t
AVWL
0
VALID
t
t
XLXL
t
LLWL
HIGH
t
XHDV
P2.0–P2.7 OR A8–A15 FROM DPH
V
t
XHQX
IH1
Figure 4. External Data Memory Write Cycle
0.8 V
2
1
Figure 5. External Clock Drive XTAL1
Figure 6. Shift Register Mode Timing
VALID
t
QVWX
t
LOW
t
XHDX
DATA OUT
t
3
DW
t
WLWH
2
VALID
t
17
CLCL
t
0.8 V
r
V
IH1
4
3
VALID
V
t
WHLH
IH1
0.8 V
t
5
WHQX
4
t
f
VALID
A0–A7 FROM PCL
A8–A15 FROM PCH
6
5
VALID
80C552/83C552
7
6
VALID
SU01696
SU01697
SU01678
INSTR IN
Product data
8
7
SET TI
SET RI
VALID