LPC2478FET208,551 NXP Semiconductors, LPC2478FET208,551 Datasheet - Page 457
LPC2478FET208,551
Manufacturer Part Number
LPC2478FET208,551
Description
IC ARM7 MCU 512K LCD 208-TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2478FET208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-TFBGA
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4364
935284072551
LPC2478FET208-S
935284072551
LPC2478FET208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FET208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
4.12 UART1 Modem Status Register (U1MSR - 0xE001 0018)
Table 408. UART1 Line Status Register (U1LSR - address 0xE001 0014, Read Only) bit
The U1MSR is a read-only register that provides status information on the modem input
signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct
affect on UART1 operation, they facilitate software implementation of modem signal
operations.
Table 409. UART1 Modem Status Register (U1MSR - address 0xE001 0018) bit description
Bit Symbol
5
6
7
Bit Symbol Value Description
0
1
2
3
4
Transmitte
r Holding
Register
Empty
Transmitte
r Empty
(TEMT)
Error in RX
FIFO
(RXFE)
Delta
CTS
Delta
DSR
Trailing
Edge RI
Delta
DCD
CTS
(THRE)
description
0
1
0
1
0
1
0
1
Value Description
0
1
0
1
0
1
Set upon state change of input CTS. Cleared on an U1MSR read.
No change detected on modem input, CTS.
State change detected on modem input, CTS.
Set upon state change of input DSR. Cleared on an U1MSR read.
No change detected on modem input, DSR.
State change detected on modem input, DSR.
Set upon low to high transition of input RI. Cleared on an U1MSR
read.
No change detected on modem input, RI.
Low-to-high transition detected on RI.
Set upon state change of input DCD. Cleared on an U1MSR read.
No change detected on modem input, DCD.
State change detected on modem input, DCD.
Clear To Send State. Complement of input signal CTS. This bit is
connected to U1MCR[1] in modem loopback mode.
Rev. 04 — 26 August 2009
THRE is set immediately upon detection of an empty UART1
THR and is cleared on a U1THR write.
U1THR contains valid data.
U1THR is empty.
TEMT is set when both U1THR and U1TSR are empty; TEMT is
cleared when either the U1TSR or the U1THR contain valid data.
U1THR and/or the U1TSR contains valid data.
U1THR and the U1TSR are empty.
U1LSR[7] is set when a character with a RX error such as framing
error, parity error or break interrupt, is loaded into the U1RBR.
This bit is cleared when the U1LSR register is read and there are
no subsequent errors in the UART1 FIFO.
U1RBR contains no UART1 RX errors or U1FCR[0]=0.
UART1 RBR contains at least one UART1 RX error.
Chapter 17: LPC24XX UART1
UM10237
© NXP B.V. 2009. All rights reserved.
457 of 792
Reset
Value
0
0
0
0
0
Reset
Value
1
1
0
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