EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet
EP9307-IRZ
Specifications of EP9307-IRZ
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EP9307-IRZ Summary of contents
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... SDRAM I/F Flash I/F MEMORY AND STORAGE Copyright 2010 Cirrus Logic (All Rights Reserved) EP9307 Data Sheet Touchscreen Interface with ADC Keypad Scanner One Serial Peripheral Interface (SPI) Port 6-channel or 2-channel Serial Audio Interface (I 2-channel, Low-cost Serial Audio Interface (AC'97) ...
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... A three-port USB 2.0 Full-speed Host (OHCI) (12 Mbits per second) and three UARTs are included as well. The EP9307 is a high-performance, low-power, RISC- based, single-chip computer built around an ARM920T microprocessor core with a maximum operating clock rate of 200 MHz (184 MHz for industrial conditions). The ARM core operates from a 1 ...
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... ADC ........................................................................................................................... 38 JTAG .......................................................................................................................... 39 272 Pin TFBGA Package Outline ...................................................................40 272 TFBGA Diagram ................................................................................................. 40 272 Pin TFBGA Pinout (Bottom View) ....................................................................... 41 Acronyms and Abbreviations ........................................................................48 Units of Measurement .....................................................................................48 ORDERING INFORMATION ............................................................................49 DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen Copyright 2010 Cirrus Logic (All Rights Reserved) EP9307 3 ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen List of Figures Figure 1. Timing Diagram Drawing Key ................................................................................. 14 Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 15 Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 16 Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 17 Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 18 Figure 6 ...
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... Table P. Reset and Power Management Pin Assignments ................................................... 11 Table Q. Hardware Debug Interface ...................................................................................... 11 Table R. 272 Pin Diagram Dimensions .................................................................................. 41 Table S. Pin Descriptions ..................................................................................................... 46 Table T. Pin Multiplex Usage Information ............................................................................. 47 DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen Copyright 2010 Cirrus Logic (All Rights Reserved) EP9307 5 ...
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... EP9307 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP9307 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’ ...
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... AC'97 Reset AC'97 Reset I2S Master Clock AC'97 Bit Clock I2S Serial Clock AC'97 Frame AC'97 Frame I2S Frame Clock Clock Clock AC'97 Serial AC'97 Serial Input I2S Serial Input Input AC'97 Serial AC'97 Serial I2S Serial Output Output Output EP9307 Mode 7 ...
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... Composite Blank BRIGHT Pulse Width Modulated Brightness Graphics Accelerator The EP9307 contains a hardware graphics acceleration engine that improves graphic performance by handling block copy, block fill and hardware line draw operations. The Graphics Accelerator is used in the system to off- load graphics operations from the processor. ...
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... UART3 Receive TENn HDLC3 Transmit Enable Internal Boot ROM The Internal 16-kbyte ROM allows booting from FLASH memory, SPI or UART. Consult the EP9307 User’s Guide for operational details. DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen Triple-port USB Host ...
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... KHz input clock. This compensation is accurate to ±1.24 sec/month. Note: A real time clock must be connected to RTCXTALI or the EP9307 device will not boot. Table K. Real-Time Clock with Pin Assignments Pin Mnemonic Pin Name - Description RTCXTALI Real-Time Clock Oscillator Input ...
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... DMA channel, source and destination addressing can be independently programmed to increment, DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen decrement, or stay at the same value. All DMA addresses are physical, not virtual addresses. Two of these are can be used Copyright 2010 Cirrus Logic (All Rights Reserved) EP9307 11 ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Electrical Specifications Absolute Maximum Ratings (All grounds = 0 V, all voltages with respect Parameter Power Supplies Total Power Dissipation Input Current per Pin, DC (Except supply pins) Output current per pin, DC Digital Input voltage ...
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... RVDD Copyright 2010 Cirrus Logic (All Rights Reserved) Symbol Min Max 0.85 × RVDD 0.15 × RVDD 0.65 × RVDD V VDD + 0.3 ih −0.3 0.35 × RVDD -10 il Min Typ Max - 190 240 - 3.5 - 1.0 2 EP9307 Unit µA µA Unit Table ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Timings Timing Diagram Conventions This data sheet contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated ...
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... Figure 2. SDRAM Load Mode Register Cycle Timing Measurement DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen Symbol t clk_high t clk_low t clkrf DQd t DQh t DAs t DAh OP-Code Copyright 2010 Cirrus Logic (All Rights Reserved) Min Typ Max ( HCLK ( HCLK - clk_low clk_high EP9307 Unit ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen SDRAM Burst Read Cycle SDCLK t d SDCSn RASn CASn SDWEn t DQd DQMn DQMn clk_low DAs DAh n t DAs Figure 3. SDRAM Burst Read Cycle Timing Measurement Copyright 2010 Cirrus Logic (All Rights Reserved) ...
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... SDRAM Burst Write Cycle SDCLK t d SDCSn RASn CASn SDWEn DQMn DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen t clk_low Figure 4. SDRAM Burst Write Cycle Timing Measurement Copyright 2010 Cirrus Logic (All Rights Reserved) EP9307 t clk_high t clkrf ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen SDRAM Auto Refresh Cycle SDCLK SDCSn RASn CASn SDWEn Note: Chip select shown as bus to illustrate multiple devices being put into auto refresh in one access Figure 5. SDRAM Auto Refresh Cycle Timing Measurement 18 t clk_low ...
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... ARM9 SOC with Ethernet, USB, Display and Touchscreen Symbol Min t 0 ADs t t ADh HCLK t - RDpw t - RDd t - DQMd + DAs HCLK t 0 DAh t ADs t RDd t DQMd Copyright 2010 Cirrus Logic (All Rights Reserved) Typ Max - - - - × (WST1 + HCLK - ADh t RDd t t DAs EP9307 Unit DAh 19 ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Static Memory Single Word Write Cycle Parameter AD setup to WRn assert time AD hold from WRn deassert time WRn deassert to CSn deassert time CSn to WRn assert delay time WRn assert time CSn to DQMn assert delay time ...
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... DAh2 t t AD2 t DAh1 t DAs1 Copyright 2010 Cirrus Logic (All Rights Reserved) Typ Max - - × (WST1 + HCLK × (WST1 + HCLK × (WST1 + HCLK - - × (4 × WST1 + 5) - HCLK - AD2 AD3 t RDd DAh1 DAh1 t t DAs1 EP9307 Unit ADh t DAh2 DAs2 21 ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Static Memory 32-bit Write on 8-bit External Bus Parameter AD setup to WRn assert time WRn/DQMn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time ...
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... DAs1 DAs2 HCLK t 0 DAh1 t 0 DAh2 t ADd1 t RDpwl t DQMd t DAs1 Copyright 2010 Cirrus Logic (All Rights Reserved) Typ Max - - × (WST1 + HCLK × (WST1 + HCLK - - × ((2 × WST1 ADd2 t RDh t DQMh t t DAh1 DAs2 EP9307 Unit ADh t DAh2 23 ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Static Memory 32-bit Write on 16-bit External Bus Parameter AD setup to WRn assert time WRn/DQMn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time ...
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... DAh2 t ADd2 t DAh1 t t DAs1 DAs1 Copyright 2010 Cirrus Logic (All Rights Reserved) Typ Max × (WST1 + 1) t HCLK × (WST2 + 1) t HCLK × (WST1 + 2) t HCLK - - - - - - - t t ADd2 ADd3 t t DAh1 DAh1 t t DAs1 DAs2 EP9307 Unit - ADh t DAh2 25 ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Static Memory Burst Write Cycle Parameter AD setup to WRn assert time AD hold from WRn deassert time WRN/DQMn deassert to AD transition time CSn hold from WRn deassert time CSn to WRn assert delay time CSn to DQMn assert delay time ...
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... DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen Symbol Min t - WAITd × WAITpw HCLK × CSnd HCLK t WAITd t WAITpw Copyright 2010 Cirrus Logic (All Rights Reserved) Typ Max × (WST1- HCLK × 510 t - HCLK × HCLK t CSnd EP9307 Unit ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Static Memory Single Write Wait Cycle Parameter WAIT to WRn deassert delay time CSn assert to WAIT time WAIT assert time WAIT to CSn deassert delay time AD CSn WRn RDn DQMn DA WAIT Figure 15. Static Memory Single Write Wait Cycle Timing Measurement ...
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... CSnY WRn RDn DQMn DA WAIT Figure 16. Static Memory Turnaround Cycle Timing Measurement DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen Symbol Min t - BTcyc t BTcyc Copyright 2010 Cirrus Logic (All Rights Reserved) Typ Max × (IDCY+ HCLK EP9307 Unit ns 29 ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Ethernet MAC Interface Parameter TXCLK cycle time TXCLK high time TXCLK low time TXCLK to signal transition delay time TXCLK rise/fall time RXCLK cycle time RXCLK high time RXCLK low time RXDVAL / RXERR setup time ...
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... MDC MDIO (Sourced by PHY) DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen t t TX_high TX_low t TX_per t RXh t RXs t MDC_low t MDIOd Figure 17. Ethernet MAC Timing Measurement Copyright 2010 Cirrus Logic (All Rights Reserved RX_low RX_high t RX_per t t MDIOs MDIOh EP9307 31 ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Audio Interface The following table contains the values for the timings of each of the SPI modes. Parameter SCLK cycle time SCLK high time SCLK low time SCLK rise/fall time Data from master valid delay time ...
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... SSPRXD DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen t clkrf t clk_low LSB bits Figure 18. TI Single Transfer Timing Measurement LSB 0 MSB bits output data Figure 19. Microwire Frame Format, Single Transfer Copyright 2010 Cirrus Logic (All Rights Reserved) EP9307 LSB 33 ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Motorola SPI t clk_high SCLK (SPO=0) SCLK (SPO=1) t DMs SSPTXD MSB (master) t DMd t DSs SSPRXD MSB (slave) SFRM 34 t clk_per t clk_low t DMh t DSh Figure 20. SPI Format with SPH=1 Timing Measurement Copyright 2010 Cirrus Logic (All Rights Reserved) ...
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... ARM9 SOC with Ethernet, USB, Display and Touchscreen Symbol t clk_per t clk_high t clk_low t clkrf t LRd t LRh t SDIs t SDIh t SDOd t SDOh t clk_low t t LRd LRh t SDIs t SDOd 2 Figure 21. Inter-IC Sound (I S) Timing Measurement Copyright 2010 Cirrus Logic (All Rights Reserved) EP9307 Min Typ Max Unit i2s_clk ( i2s_clk ( i2s_clk ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen AC’97 Parameter ABITCLK input cycle time ABITCLK input high time ABITCLK input low time ABITCLK input rise/fall time ASDI setup to ABITCLK falling ASDI hold after ABITCLK falling ASDI input rise/fall time ABITCLK rising to ASDO / ASYNC valid, C ...
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... SPCLK rising edge to data transition time Data valid time SPCLK HSYNC/ V_CSYNC/ BLANK/ BRIGHT [17:0] DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen Symbol t clkr clkrf Figure 23. LCD Timing Measurement Copyright 2010 Cirrus Logic (All Rights Reserved) Min Typ Max SPCLK t clkrf EP9307 Unit ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen ADC Parameter Resolution Integral non-linearity Offset error Full scale error Maximum sample rate Channel switch settling time Noise (RMS) - typical Note: ADIV refers to bit 16 in the KeyTchClkDiv register. ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4. ...
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... JPzx TDO DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen t JPs t JPco Figure 25. JTAG Timing Measurement Copyright 2010 Cirrus Logic (All Rights Reserved) Symbol Min Max t 100 - clk_per clk_high clk_low JPs JPh JPco JPzx JPxz t JPh t JPxz EP9307 Units ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen 272 Pin TFBGA Package Outline 272 TFBGA Diagram D 40 Figure 26. 272 Pin TFBGA Diagram 0.600 REF ddd ddd Copyright 2010 Cirrus Logic (All Rights Reserved Øb DS667F2 ...
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... Figure 26, "272 Pin TFBGA Diagram", on page Copyright 2010 Cirrus Logic (All Rights Reserved) dimension in inches NOM MAX 0.055 0.057 0.011 0.013 0.028 0.030 0.016 0.018 0.0102 0.0122 0.551 0.553 0.504 0.506 0.551 0.553 0.504 0.506 0.031 0.033 0.004 EP9307 40. 41 ...
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P[8] P[4] P[ V_CSYNC P[7] P[2] R P[9] HSYNC P[6] P[5] P[0] P SPCLK P[10] P[11] P[3] AD[15] N P[14] P[16] P[15] P[13] P[12] M BRIGHT AD[0] DQMn[1] DQMn[2] ...
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... DA[8] R9 DTRn BLANK R10 TDI gndr R11 BOOT[0] gndr R12 ASYNC ROW[7] R13 SSPTX[1] ROW[5] R14 PWMOUT PLL_GND R15 USBm[0] XTALI R16 ABITCLK XTALO R17 USBp[0] BRIGHT T1 NC AD[ DQMn[1] T3 V_CSYNC DQMn[2] T4 P[7] P[17] T5 P[2] gndr T6 DA[7] gndr T7 AD[11] vddc T8 AD[9] EP9307 43 ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Ball Signal Ball C9 MDIO G14 C10 MIIRXD[2] G15 C11 TXCLK G16 C12 MIITXD[0] G17 C13 CLD H1 C14 EGPIO[13] H2 C15 TRSTn H3 C16 Xp H4 C17 SDCSn[ DA[23 SDCLK H9 D4 DA[24] H10 D5 HGPIO[7] H12 D6 HGPIO[6] ...
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... The second table (Table signal multiplexing and configuration options. Table summary of the EP9307 pin signals, which illustrates the pad type and pad pull type (if any). The symbols used in the table are defined as follows. (Note: A blank box means Not Applicable (NA) or, for Pull Type, No Pull (NP) ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen . Table S. Pin Descriptions Pad Pull Pin Name Block Type Type TCK JTAG I PD JTAG clock in TDI JTAG I PD JTAG data in TDO JTAG 4ma - JTAG data out TMS JTAG I PD JTAG test mode select ...
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... Copyright 2010 Cirrus Logic (All Rights Reserved) Multiplex signal name GPIO Port D[7:0] GPIO Port C[7:0] RI CLK1HZ DMARQ HDLCCLK1 SDO1 SDI1 SDO2 DREQ0 DACK0 DEOT0 DREQ1 DACK1 DEOT1 SDI2 DASP SCLK LRCK SDO0 SDI0 MCLK SCLK LRCK SDO0 SDI0 EP9307 47 ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Acronyms and Abbreviations The following tables list abbreviations and acronyms used in this data sheet. Term Definition ADC Analog-to-Digital Converter ALT Alternative AMBA Advanced Micro-controller Bus Architecture ATAPI ATA Packet Interface CODEC COder / DECoder ...
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... ORDERING INFORMATION The order numbers for the device are: EP9307-CRZ EP9307-IRZ -40°C to +85°C EP9307 — CRZ Part Number Product Line: Embedded Processor Note the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative. DS667F2 ARM9 SOC with Ethernet, USB, Display and Touchscreen 0° ...
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... EP9307 ARM9 SOC with Ethernet, USB, Display and Touchscreen Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided " ...