EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 7

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

Ethernet Media Access Controller (MAC)
The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:
•
•
Serial Interfaces (SPI, I
The SPI port can be configured as a master or a slave,
supporting the National Semiconductor
Texas Instruments
The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. The I
be configured to support two channel, 24 bit audio.
These ports are multiplexed so that I
over either the AC'97 pins or the SPI pins. The second
and third I2S ports' serial input and serial output pins are
multiplexed with EGPIO[4,5,6,13]. The clocks supplied in
the first I2S port are also used for the second and third
I2S ports.
•
•
•
DS667F2
MDC
MDIO
RXCLK
MIIRXD[3:0]
RXDVAL
RXERR
TXCLK
MIITXD[3:0]
TXEN
TXERR
CRS
CLD
Table C. Ethernet Media Access Controller Pin Assignments
Supports 1/10/100 Mbps transfer rates for
home/small-business/large-business applications
Interfaces to an off-chip PHY through industry
standard Media Independent Interface (MII)
Normal Mode: One SPI Port and one AC’97 Port
I
Ports
I
Ports
Note:
Pin Mnemonic
2
2
S on SSP Mode: One AC’97 Port and up to three I
S on AC’97 Mode: One SPI Port and up to three I
I
same time.
2
S may not be output on AC’97 and SSP ports at the
®
signaling protocols.
Management Data Clock
Management Data I/O
Receive Clock
Receive Data
Receive Data Valid
Receive Data Error
Transmit Clock
Transmit Data
Transmit Enable
Transmit Error
Carrier Sense
Collision Detect
2
S and AC ’97)
Pin Description

Copyright 2010 Cirrus Logic (All Rights Reserved)
2
®
S port 0 will take
, Motorola
2
S port can
®
, and
2
2
S
S
Raster/LCD Interface
The Raster/LCD interface provides data and interface
signals for a variety of display types. It features fully
programmable video interface timing for non-interlaced
flat panel or dual scan displays. Resolutions up to
1024 x 768 are supported from a unified SDRAM based
frame buffer. A 16-bit PWM provides control for LCD
panel contrast. LCD specific features include:
•
•
•
•
•
•
•
•
SCLK1
SFRM1
SSPRX1 SPI Serial Input
SSPTX1
ARSTn
ABITCLK AC'97 Bit Clock
ASYNC
ASDI
ASDO
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Name
Pin
Timing and interface signals for digital LCD and TFT
displays
Full programmability for either non-interlaced or dual-
scan color and grayscale flat panel displays
Dedicated data path to SDRAM controller for
improved system performance
Pixel depths of 4, 8, 16, or 24 bits per pixel or 256
levels of grayscale
Hardware Cursor up to 64 x 64 pixels
256 x 18 Color Lookup Table
Hardware Blinking
8-bit interface to low-end panel
SPI Bit Clock
SPI Frame Clock I2S Frame Clock
SPI Serial
Output
AC'97 Reset
AC'97 Frame
Clock
AC'97 Serial
Input
AC'97 Serial
Output
Normal Mode
Description
Table D. Audio Interfaces Pin Assignment
Pin
I2S Serial Clock
I2S Serial Input
I2S Serial Output
(No I2S Master
Clock)
AC'97 Reset
AC'97 Bit Clock
AC'97 Frame
Clock
AC'97 Serial Input I2S Serial Input
AC'97 Serial
Output
Pin Description Pin Description
I2S on SSP
Mode
SPI Bit Clock
SPI Frame Clock
SPI Serial Input
SPI Serial Output
I2S Master Clock
I2S Serial Clock
I2S Frame Clock
I2S Serial Output
I2S on AC'97
Mode
EP9307
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