EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 3

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

HDLC
SDRAM Controller
ER667E2B
Description
When the final byte of a received packet is read into the DMA controller's buffer, the software will be notified
by an HDLC RFC interrupt. However, the DMA controller may not have written the currently buffered part of
the packet to memory, so that the last one to fifteen bytes of a packet may not be accessible.
Workaround
To insure that the DMA channel empties the buffer, do the following (in the HDLC interrupt handler, for
example):
1) Note the values in the MAXCNTx and REMAIN registers for the DMA channel. The difference is the num-
2) Temporarily disable the UART DMA RX interface by clearing the RXDMAE bit in the UART1DMACtrl reg-
3) Wait until the difference between the CURRENTx and BASEx registers in the DMA channel is equal to
At this point, the rest of the packet is guaranteed to have been written to memory. Using this method will
cause an extra byte to be read from the UART by the DMA channel and also written to memory. This last
byte should be ignored.
Description 1
Using the SDRAM controller in auto-precharge mode will produce system instability at external bus speeds
greater than 50MHz.
Workaround
Do not turn on the auto-precharge feature of the SDRAM controller if the external bus speed will be greater
than 50 MHz.
Description 2
When the SDRAM controller is configured for PRECHARGE ALL command, the actual sequence is not
always issued to the SDRAM device(s).
Workaround
Do a read from each SDRAM bank so that a PRECHARGE command is issued to each bank of the SDRAM
device. This will satisfy the required SDRAM initialization sequence.
Due to the effectiveness and simplicity of the software workaround, no silicon fix is planned.
ber of bytes read from the UART/HDLC, which is the size of the HDLC packet. Call this number N. Note
that the BC field of the UART1HDLCRXInfoBuf register should also be N.
ister.
N + 1.
3