STM8S103F3U6TR STMicroelectronics, STM8S103F3U6TR Datasheet - Page 42
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
STM8S103F3U6TR
Manufacturer Part Number
STM8S103F3U6TR
Description
MCU 8BIT 8KB FLASH 20-UFQFPN
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet
1.STM8S103F2P6TR.pdf
(113 pages)
Specifications of STM8S103F3U6TR
Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
640 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VFQFN, 20-VFQFPN
Processor Series
STM8S10x
Core
STM8
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STM8/128-MCKIT, STM8S-DISCOVERY, ST-LINK, STICE-SYS001, STX-RLINK
For Use With
497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8S103F3U6TR
Manufacturer:
MAXIM
Quantity:
1 400
Company:
Part Number:
STM8S103F3U6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Option bytes
8
42/113
Addr.
0x4800
0x4801
0x4802
0x4803
0x4804
0x4805h
0x4806
0x4807
0x4808
0x4809
0x480A
Option
name
Read-out
protection
(ROP)
User boot
code(UBC)
Alternate
function
remapping
(AFR)
Miscell.
option
Clock
option
HSE clock
startup
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Option byte no.
OPT0
Option
byte no.
OPT0
OPT1
NOPT1
OPT2
NOPT2
OPT3
NOPT3
OPT4
NOPT4
OPT5
NOPT5
Option bits
7
ROP [7:0]
UBC [7:0]
NUBC [7:0]
AFR7
NAFR7
Reserved
Reserved
Reserved
Reserved
HSECNT [7:0]
NHSECNT [7:0]
Description
6
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
AFR6
NAFR6
Table 11: Option bytes
Table 12: Option byte description
DocID15441 Rev 6
5
AFR5
NAFR5
4
AFR4
NAFR4
HSI
TRIM
NHSI
TRIM
STM8S103K3 STM8S103F3 STM8S103F2
3
AFR3
NAFR3
LSI_ EN
NLSI_
EN
EXT CLK
NEXT
CLK
2
AFR2
NAFR2
IWDG
_HW
NIWDG
_HW
CKAWU
SEL
NCKA
WUSEL
1
AFR1
NAFR1
WWDG
_HW
NWWDG
_HW
PRS C1
NPRSC1
0
AFR0
NAFR0
WWDG
_HALT
NWW
G_HALT
PRS C0
NPR
SC0
Factory
default
setting
00h
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh