ST7FLITEU09M3TR STMicroelectronics, ST7FLITEU09M3TR Datasheet - Page 25

• Manufacturer Part Number: ST7FLITEU09M3TR
• Description: IC MCU 8BIT 2K FLASH 8SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU09M3TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Details

ST7LITEU05 ST7LITEU09
5.4
5.4.1
5.4.2
5.4.3
5.5
Figure 9.
1. If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not
Power saving modes
Wait mode
The data EEPROM can enter Wait mode on execution of the WFI instruction of the
microcontroller or when the microcontroller enters Active-Halt mode.The DATA EEPROM
will immediately enter this mode if there is no programming in progress, otherwise the data
EEPROM will finish the cycle and then enter Wait mode.
Active-halt mode
Refer to Wait mode.
Halt mode
The data EEPROM immediately enters Halt mode if the microcontroller executes the HALT
instruction. Therefore the EEPROM will stop the function in progress, and data may be
corrupted.
Access error handling
If a read access occurs while E2LAT=1, then the data bus will not be driven.
If a write access occurs while E2LAT=0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by a Reset action), the integrity of the data in memory
will not be guaranteed.
E2LAT bit
E2PGM bit
guaranteed.
DEFINITION
ROW
Data EEPROM write operation
Byte 1
Set by USER application
Writing data latches
Row / byte
Byte 2
PHASE 1
...
N
0
1
Read operation impossible
Byte 32
0 1 2 3
Waiting E2PGM and E2LAT to fall
Programming cycle
PHASE 2
...
30
31
Read operation possible
Cleared by hardware
Nx20h...Nx20h+1Fh
Physical address
00h...1Fh
20h...3Fh
Data EEPROM
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