ST7FLITE39F2M3TR STMicroelectronics, ST7FLITE39F2M3TR Datasheet - Page 16

• Manufacturer Part Number: ST7FLITE39F2M3TR
• Description: IC MCU 8BIT 8K FLASH 20SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE39F2M3TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: 497-8406 - BOARD STF20NM50FD/STF7LITE39BF2497-8403 - BOARD DEMO STCC08 AC SW DETECTOR497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE3xF2
DATA EEPROM (Cont’d)
5.3 MEMORY ACCESS
The Data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in
access modes.
Read Operation (E2LAT=0)
The EEPROM can be read as a normal ROM loca-
tion when the E2LAT bit of the EECSR register is
cleared.
On this device, Data EEPROM can also be used to
execute machine code. Take care not to write to
the Data EEPROM while executing from it. This
would result in an unexpected code being execut-
ed.
Write Operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be
set by software (the E2PGM bit remains cleared).
When a write access to the EEPROM area occurs,
Figure 7. Data EEPROM Programming Flowchart
16/173
1
Figure 7
describes these different memory
IN EEPROM AREA
READ MODE
READ BYTES
CLEARED BY HARDWARE
E2PGM=0
E2LAT=0
(with the same 11 MSB of the address)
the value is latched inside the 32 data latches ac-
cording to its address.
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 32) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the five Least
Significant Bits of the address can change.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of the
E2LAT bit.
It is not possible to read the latched data.
This note is ilustrated by the
START PROGRAMMING CYCLE
E2PGM=1 (set by software)
WRITE UP TO 32 BYTES
0
IN EEPROM AREA
WRITE MODE
E2PGM=0
E2LAT=1
E2LAT=1
E2LAT
1
Figure
9.