ST7FLIT15BM6TR STMicroelectronics, ST7FLIT15BM6TR Datasheet - Page 61

• Manufacturer Part Number: ST7FLIT15BM6TR
• Description: IC MCU 8BIT 2K FLASH SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLIT15BM6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: ST7FLIT1x
• Core: ST7
• Data Bus Width: 8 bit
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Package / Case: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3.2 Dead Time Generation
A dead time can be inserted between PWM0 and
PWM1 using the DTGR register. This is required
for half-bridge driving where PWM signals must
not be overlapped. The non-overlapping PWM0/
PWM1 signals are generated through a program-
mable dead time by setting the DTE bit.
Dead time value = DT[6:0] x Tcounter1
DTGR[7:0] is buffered inside so as to avoid de-
forming the current PWM cycle. The DTGR effect
will take place only after an overflow.
Figure 40. Dead Time Generation
In the above example, when the DTE bit is set:
– PWM goes low at DCR0 match and goes high at
– PWM1 goes high at DCR0+Tdt and goes low at
ATR1+Tdt
ATR match.
CK_CNTR1
CNTR1
PWM 1
PWM 0
PWM 0
PWM 1
counter = DCR0
DCR0
DCR0+1
T
counter1
T
dt
counter = DCR1
OVF
Notes:
1. Dead time is generated only when DTE=1 and
DT[6:0] ≠ 0. If DTE is set and DT[6:0]=0, PWM out-
put signals will be at their reset state.
2. Half Bridge driving is possible only if polarities of
PWM0 and PWM1 are not inverted, i.e. if OP0 and
OP1 are not set. If polarity is inverted, overlapping
PWM0/PWM1 signals will be generated.
3. Dead Time generation does not work at 1 ms
timebase.
With this programmable delay (Tdt), the PWM0
and PWM1 signals which are generated are not
overlapped.
T
dt
= DT[6:0] x T
ATR1
counter1
T
dt
ST7LITE1xB
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