ST7FLITE35F2M6 STMicroelectronics, ST7FLITE35F2M6 Datasheet - Page 52

• Manufacturer Part Number: ST7FLITE35F2M6
• Description: IC MCU 8BIT 8K FLASH 20SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE35F2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7FLITE3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5085 - EVAL BOARD UNIV MOTOR CONTROL497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Function Descriptions
Table 28. SCI2_ClkConfigure
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Function Name
Function Prototype
Behaviour Description
Input Parameter 1
Input Parameter 2
Output Parameters
Required Preconditions.
Functions called
Postconditions
See also
Void SCI2_ClkConfigure(SCI_PO_PH_t
SCI_PO_PH_Param, SCI_LBCL_t SCI_LBCL_Param)
Configures the Polarity, Phase and numbers of Clock
pulses for the SCI2 Clock out.
SCI_PO_LOW_PH_LOW
Default value on CLK pin low
CLK activated at the in the middle of data bit
SCI_PO_LOW_PH_HIGH
Default value on CLK pin low
CLK activated at the beginning of data bit
SCI_PO_HIGH_PH_LOW
Default value on CLK pin High
CLK activated in the middle of data bit
SCI_PO_HIGH_PH_HIGH
Default value on CLK pin high
CLK activated at the beginning of data bit
SCI_LBCL_DISABLE
The CLK pulse of last data bit is not output to the pin
SCI_LBCL_ENABLE
The CLK pulse of last data bit is output to the pin
None
None
None
SCI clock is availaible at a dedicated pin during communi-
cation.
None
SCI2_ClkConfigure